ST52T430/E430
4 INTERRUPTS
The Control Unit (CU) responds to peripheral
events and external events via its interrupt
channels.
When such an events occur, if the related interrupt
is not masked and according to a priority order, the
current program execution can be suspended to
allow the CU to execute a specific response
routine.
Each interrupt is associated with an interrupt
vector that contains the memory address of the
related interrupt service routine. Each vector is
located in the Program Space (EPROM Memory)
at a fixed address (see Interrupt Vectors
Table4.1 Interrupt Operation
If there are pending interrupts at the end of an
arithmetic or logic instruction, the one with the
highest priority is passed. Passing an interrupt
means storing the arithmetic flags and the current
PC in the stack and executing the associated
Interrupt routine, whose address is located in three
bytes of the EPROM memory location between
address 3 and 20.
The Interrupt routine is performed as a normal
code, checking if a higher priority interrupt has to
be passed at the end of each instruction. An
Interrupt request with the higher priority stops the
lower priority Interrupt. The Program Counter and
the arithmetic flags are stored in the stack.
With the RETI (Return from Interrupt) instruction
the arithmetic flags and Program Counter (PC) are
restored from the top of the stack. This stack was
An Interrupt request cannot stop processing of the
fuzzy rule, but this is passed only after the end of
a fuzzy rule or at the end of a logic, or arithmetic
instruction.
NOTE1: A fuzzy routine can only be interrupted
in the Main program.
However, if the fuzzy routine in the main is
interrupted by an Interrupt routine containing
another
fuzzy
routine,
the
internal
fuzzy
registers used for the first are modified with
results of the latter routine.
NOTE2: It is recommended not to interrupt a
Fuzzy function contained in an Interrupt
routine. In order to use a Fuzzy function inside
an interrupt routine, the user MUST include the
Fuzzy function between an UDGI (MDGI)
instruction and an UEGI (MEGI) instruction
(see the following paragraphs).
Figure 4.1 Interrupt Flow
Figure 4.2 Interrupt Vectors mapping
Figure 4.3 Global Interrupt Request generation
NORMAL
PROGRAM
FLOW
INTERRUPT
SERVICE
ROUTINE
RETI
INSTRUCTION
INTERRUPT
INT_ADC
INT_TIMER/PWM2
INT_SCI
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
INTERRUPT
VECTORS
INT_EXT
18
19
20
INT_TIMER/PWM1
INT_TIMER/PWM0
Global Interrupt
Pending
User Global
Interrupt Mask
Macro Global
Global Interrupt
Request