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參數(shù)資料
| 型號： | ST52F514Y1B6 |
| 英文描述： | MAX II CPLD 240 LE 100-TQFP |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 88/106頁 |
| 文件大?。?/td> | 648K |
| 代理商： | ST52F514Y1B6 |
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Slave address transmission
At this point, the slave address is sent to the SDA
line via the internal shift register.
In 7-bit addressing mode,one addressbyteis sent.
In 10-bit addressing mode, sending the first byte
including
the
header
following event:
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Afterwards, the master waits for a read of the
I2C_SR1 register followed by a write in the
I2C_OUT register,
holding the SCL line low
(see
Figure 14.3 Transfer sequencing EV9).
The second address byte is sent by the interface.
After completionof this transfer (and acknowledge
from the slave if the ACK bit is set):
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Afterwards, the master waits for a read of the
I2C_SR1 register followed by a write in the
I2C_CR register (for example set PE bit),
holding
the SCL line low
(see Figure 14.3 Transfer
sequencing EV6).
Next,
the
master
must
Transmitter mode.
Note:
In 10-bit addressing mode, in order to switch
the master to Receiver mode, software must
generate arepeated Startcondition and resendthe
header sequence with the least significant bit set
(11110xx1).
sequence
causes
the
enter
Receiver
or
Master Receiver
Following the address transmission and after
I2C_SR1
and
I2C_CR
accessed, the master receives bytes from the SDA
line into the I2C_IN register via the internal shift
register. After each byte the interface generates in
sequence:
– Acknowledge pulse if the ACK bit is set
– EVFand BTFbits are set by hardware withan in-
terrupt if the ITE bit is set.
Afterwards, the interface waits for a read of the
I2C_SR1 registerfollowed by a read of the I2C_IN
register,
holding the SCL line low
(see Figure
14.3 Transfer sequencing EV7).
registers
have
been
In order to close the communication: before
reading the last byte from the I2C_IN register, set
the STOP bit to generate the Stop condition. The
interface automatically goes back to slave mode
(M/SL bit cleared).
Note:
In order to generate the non-acknowledge
pulse after the last data byte received, the ACK bit
must be clearedjust before readingthe secondlast
data byte.
Master Transmitter
Following the address transmission and after the
I2C_SR1 registerhas beenread, the master sends
bytes from the I2C_OUT register to the SDA line
via the internal shift register.
The master waits for a read of the I2C_SR1
register followed by a write in the I2C_OUT
register,
holding the SCL line low
(see Figure
14.3 Transfer sequencing EV8).
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
is set.
In order to close the communication: after writing
the last byte to the I2C_OUT register, set the
STOP bit to generate the Stop condition. The
interface automatically returns to slave mode (M/
SL bit cleared).
Error Cases
–
BERR
: Detection of a Stop or a Start condition
during a byte transfer.In this case, the EVF and
BERR bits are set by hardware with an interrupt
if ITE is set.
–
AF
: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
–
ARLO
: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware
(with an interrupt if the ITE bit is set and the in-
terface automatically goes back to slave mode
(the M/SL bit is cleared).
Note:
In all these cases, the SCL line is not held
low; however, the SDA line can remain low due to
possible 0 bits transmitted last. Both lines must
be released via software.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST52F514Y1M6 | IC MAX 7000 CPLD 256 256-FBGA |
| ST52F514Y3B6 | IC MAX 7000 CPLD 128 144-TQFP |
| ST52F514Y3M6 | IC MAX 7000 CPLD 256 144-TQFP |
| ST5R33 | Programmable Logic IC; Logic Type:Programmable; No. of Macrocells:102; Package/Case:144-TQFP; Leaded Process Compatible:No; Number of Circuits:1728; Peak Reflow Compatible (260 C):No; Mounting Type:surface mount RoHS Compliant: No |
| ST5R50 | ; No. of Macrocells:64; IC Generic Number:; No. of Outputs:68; Number of Inputs:68; Operating Temp. Max:70 C; Operating Temp. Min:0 C; Propagation Delay:10ns; No. of Pins:44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52F514Y1M6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514Y3B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514Y3M6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514YMM6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI |
| ST-52K | 制造商:Eaton Heinemann 功能描述:ST52K |
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