參數(shù)資料
型號(hào): ST52F510F1M6
廠商: STMICROELECTRONICS
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO20
封裝: PLASTIC, SO-20
文件頁(yè)數(shù): 46/104頁(yè)
文件大?。?/td> 644K
代理商: ST52F510F1M6
ST52F510/F513/F514
46/104
6.5 Register Description
The following section describes the Register which
are used to configure the Clock, Reset and PLVD.
6.5.1 Configuration Register.
CPU Clock Prescaler (CPU_CLK)
Configuration Register 46 (02Eh) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-6: Not Used
Bit 5-0: CPUCK5-0 CPU Clock Prescaler bits
The CPU Clock frequency is divided by a
factor described in the following table
6.5.2 Option Bytes.
Clock Mode (OSC_CR)
Option Byte 0 (00h)
Reset Value: 0000 0000 (00h)
Bit 7-2: Not Used
Bit 1-0: CKMOD1-0 Clock Mode
00: Internal Oscillator
01: External Clock or quartz
1x: External RC oscillator
External Clock Parameters (CLK_SET)
Option Byte 1 (01h)
Reset Value: 0000 0000 (00h)
Bit 7-3: Not Used
Bit 2-0: CKPAR2-0 Oscillator Gains
These three bits enable/disable the loop
gains when a external clock or quartz are
used
for
generating
the
clock.
The
following
table
decribes
the
possible
configuration options. Table 6.2 illustrates
the reccomended values for the most
common frequencies used, time to start the
oscillations and the settling time to have a
duty cycle of 40%-60% (at steady state it is
50%).
Warning: If an External Clock is used instead of a
quartz or ceramic resonator, it is reccomended that
no gain be enabled (CKPAR2-0=000) in order lo
lower the current consuption.
70
-
CPUCK5 CPUCK4 CPUCK3 CPUCK2 CPUCK1 CPUCK0
CPUCK5-0
CPU Clock
000000
fCPU=fOSC
000001
fCPU=fOSC/2
000010
fCPU=fOSC/4
000100
fCPU=fOSC/8
001000
fCPU=fOSC/16
010000
fCPU=fOSC/32
100000
fCPU=fOSC/64
others
fCPU=fOSC/64
70
-
-----
CKMOD1 CKMOD0
70
-
CKPAR2 CKPAR1 CKPAR0
CKPAR2-0
Enabled Gain Stages
000
No Gains (External Clock Mode)
001
1 gain stage enabled
010
not allowed
011
3 gain stage enabled
100
not allowed
101
4 gain stage enabled
110
not allowed
111
6 gain stage enabled
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