參數(shù)資料
型號: ST26C31IP16
英文描述: Programmable Logic IC; Logic Type:Programmable; No. of Macrocells:246; Package/Case:356-BGA; Leaded Process Compatible:No; Number of Circuits:1728; Peak Reflow Compatible (260 C):No RoHS Compliant: No
中文描述: 線路驅動器
文件頁數(shù): 2/8頁
文件大?。?/td> 72K
代理商: ST26C31IP16
ST26C31
2
Rev. 1.01
PIN CONFIGURATION
16 Lead PDIP (0.300”)
V
CC
INPUT D
OUTPUT D+
OUTPUT D-
-ENABLE
OUTPUT C-
OUTPUT C+
INPUT C
INPUT A
OUTPUT A+
OUTPUT A-
ENABLE
OUTPUT B-
OUTPUT B+
INPUT B
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
16 Lead SOIC (Jedec, 0.150”)
16
1
9
8
2
3
4
5
6
7
15
14
13
12
11
10
V
CC
INPUT D
OUTPUT D+
OUTPUT D-
-ENABLE
OUTPUT C-
OUTPUT C+
INPUT C
INPUT A
OUTPUT A+
OUTPUT A-
ENABLE
OUTPUT B-
OUTPUT B+
INPUT B
GND
PIN DESCRIPTION
Pin #
Symbol
Type
Description
1
INPUT A
I
Driver A input pin.
2
OUTPUT A+
O
Driver A differential non-inverting output pin.
3
OUTPUT A-
O
Driver A differential inverting output pin.
4
ENABLE
I
Gate control (active high). This pin is one of the two control pins which enables or disables
all four drivers. All four drivers are gated with two input or gate.
Driver B differential inverting output pin.
5
OUTPUT B-
O
6
OUTPUT B+
O
Driver B differential non-inverting output pin.
7
INPUT B
I
Driver B input pin.
8
GND
O
Signal and power ground.
9
INPUT C
I
Driver C input pin.
10
OUTPUT C+
O
Driver C differential non-inverting output pin.
11
OUTPUT C-
O
Driver C differential inverting output pin.
12
-ENABLE
I
Gate control (active low). See ENABLE pin description.
13
OUTPUT D-
O
Driver D differential inverting output pin.
14
OUTPUT D+
O
Driver D differential non-inverting output pin.
15
INPUT D
I
Driver D input pin.
16
V
CC
I
Power supply pin.
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