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參數(shù)資料
| 型號： | ST24FW21B1 |
| 英文描述： | IC ACEX 1K FPGA 100K 484-FBGA |
| 中文描述： | I2C串行EEPROM的 |
| 文件頁數(shù)： | 14/21頁 |
| 文件大?。?/td> | 152K |
| 代理商： | ST24FW21B1 |
Page Write.
The Page Write mode allows up to 8
bytes to be written in a single write cycle, provided
that they are all located in the same ’row’ in the
memory: that is the most significant memory ad-
dress bits are the same. The master sends from
one up to 8 bytes of data, which are each acknow-
ledged by the memory.
After each byte is transfered, the internal byte
address counter (3 least significant bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition. Care must be
taken to avoid address counter ’roll-over’ which
could result in data being overwritten. Note that, for
any write mode, the generation by the master of the
STOP condition starts the internal memory pro-
gram cycle. All inputs are disabled until the comple-
tion of this cycle and the memory will not respond
to any request.
Minimizing System Delays by Polling On ACK
.
During the internal write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (t
W
) is given in the
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re-
duced by an ACK polling sequence issued by the
master. The sequence is as follows:
– Initial condition: a Write is in progress (see Fig-
ure 10).
– Step 1: the Master issues a START condition
followed by a Device Select byte (1st byte of
the new instruction).
S
S
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
S
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1
DATA IN 2
AI01893
S
DATA IN N
ACK
ACK
ACK
R/W
ACK
ACK
ACK
R/W
ACK
ACK
VCLK/WC
VCLK/WC
Figure 11. Write Modes Sequence
14/21
ST24LC21B, ST24LW21, ST24FC21, ST24FW21
相關PDF資料 |
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| ST24FW21B6 | IC MAX 7000 CPLD 32 44-PLCC |
| ST24LC21B1 | Stratix II FPGA 180K FBGA-1508 |
| ST24LC21M1 | IC CONFIG DEVICE 1.6MBIT 20-PLCC |
| ST24XY21 | IC MAX 7000 CPLD 128 84-PLCC |
| ST24LW21B6TR | 1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ST24FW21B1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
| ST24FW21B6 | 功能描述:電可擦除可編程只讀存儲器 Dual Mode 1K (128x8) RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| ST24FW21B6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
| ST24FW21M1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| ST24FW21M1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
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