REV. 5.0.2 12 2.7 Crystal Oscillator or External Clock Input The 654 includes an on-" />
參數(shù)資料
型號： ST16C654IQ64-F
廠商： Exar Corporation
文件頁數(shù)： 4/51頁
文件大小： 0K
描述： IC UART FIFO 64B QUAD 64LQFP
標準包裝： 160
特點： *
通道數(shù)： 4，QUART
FIFO's： 64 字節(jié)
規(guī)程： RS232
電源電壓： 2.97 V ~ 5.5 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應商設備封裝： 64-LQFP（10x10）
包裝： 托盤
其它名稱： 1016-1273
ST16C654/654D
xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.2
12
2.7
Crystal Oscillator or External Clock Input
The 654 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see “Section
FIGURE 5. TYPICAL OSCILLATOR CONNECTIONS
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins. Typical oscillator connections are shown
in Figure 5. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate
generator for standard or custom rates. For further reading on oscillator circuit please see application note
DAN108 on EXAR’s web site.
2.8
Programmable Baud Rate Generator
Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a
software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external
clock by 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a
programmable divisor between 1 and (216 -1) to obtain a 16X sampling rate clock of the serial data rate. The
sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling.
TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D
PINS
FCR BIT-0=0
(FIFO DISABLED)
FCR BIT-0=1 (FIFO ENABLED)
FCR BIT-3 = 0
(DMA MODE DISABLED)
FCR BIT-3 = 1
(DMA MODE ENABLED)
RXRDY#
0 = 1 byte
1 = no data
0 = at least 1 byte in FIFO
1 = FIFO empty
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
TXRDY#
0 = THR empty
1 = byte in THR
0 = FIFO empty
1 = at least 1 byte in FIFO
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
C1
22-47pF
C2
22-47pF
14.7456
MHz
XTAL1
XTAL2
R=300K to 400K
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