參數(shù)資料
型號(hào): ST16C654DIQ64
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
中文描述: 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64
文件頁數(shù): 24/51頁
文件大?。?/td> 968K
代理商: ST16C654DIQ64
ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
24
4.0
INTERNAL REGISTER DESCRIPTIONS
4.1
See “Receiver” on page15.
4.2
Transmit Holding Register (THR) - Write-Only
See “Transmitter” on page13.
4.3
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.3.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A.
2(23
'""
'' % (
2(23
'"" '' %
B.
2(23
! ( '
2(23 '' % ) ( '
2(23
'' %
C.
4 )(0
2(23% ( 2(23 "%
Receive Holding Register (RHR) - Read- Only
!
!" !
'
Enhanced Registers
0 1 0
EFR
RD/WR
Auto
CTS#
Enable
Auto
RTS#
Enable
Special
Char
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
Soft-
ware
Flow
Cntl
Bit-3
Soft-
ware
Flow
Cntl
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Soft-
ware
Flow
Cntl
Bit-0
LCR=0
X
BF
1 0 0
XON1
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 0 1
XON2
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 0
XOFF1 RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 1
XOFF2 RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
X X X
FSTAT
RD
RX-
RDYD#
RX-
RDYC#
RX-
RDYB#
RX-
RDYA#
TX-
RDYD#
TX-
RDYC#
TX-
RDYB#
TX-
RDYA#
FSRS# pin is
a logic 0. No
address lines
required.
T
ABLE
10: INTERNAL REGISTERS DESCRIPTION.
S
HADED
BITS
ARE
ENABLED
WHEN
EFR B
IT
-4=1
A
DDRESS
A2-A0
R
EG
N
AME
R
EAD
/
W
RITE
B
IT
-7
B
IT
-6
B
IT
-5
B
IT
-4
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
C
OMMENT
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