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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ST16C654CQ64-F |
| 寤犲晢锛� | Exar Corporation |
| 鏂囦欢闋佹暩(sh霉)锛� | 11/51闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC UART FIFO 64B QUAD 64LQFP |
| 妯欐簴鍖呰锛� | 160 |
| 鐗归粸锛� | * |
| 閫氶亾鏁�(sh霉)锛� | 4锛孮UART |
| FIFO's锛� | 64 瀛楃瘈(ji茅) |
| 瑕�(gu墨)绋嬶細 | RS232 |
| 闆绘簮闆诲锛� | 2.97 V ~ 5.5 V |
| 甯惰嚜鍕曟祦閲忔帶鍒跺姛鑳斤細 | 鏄� |
| 甯禝rDA 绶ㄧ⒓鍣�/瑙ｇ⒓鍣細 | 鏄� |
| 甯舵晠闅滃暉鍕曚綅妾㈡脯鍔熻兘锛� | 鏄� |
| 甯惰(di脿o)鍒惰В瑾�(di脿o)鍣ㄦ帶鍒跺姛鑳斤細 | 鏄� |
| 甯禖MOS锛� | 鏄� |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 64-LQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 64-LQFP锛�10x10锛� |
| 鍖呰锛� | 鎵樼洡 |
| 鍏跺畠鍚嶇ū锛� | 1016-1445 ST16C654CQ64-F-ND |
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ST16C654/654D
REV. 5.0.2
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
19
2.15
Infrared Mode
The 654 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)
version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGH-
pulse for each 鈥�0鈥� bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED,
hence reduces the power consumption. See Figure 12 below.
The infrared encoder and decoder are enabled by setting MCR register bit-6 to a 鈥�1鈥�. When the infrared feature
is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level
of logic zero from a reset and power up, see Figure 12.
Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.
Each time it senses a light pulse, it returns a logic 1 to the data bit stream.
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
Character
Data Bits
Start
Stop
00
0
11
1 1
1
Bit Time
1/16 Clock Delay
IRdecoder-
RX Data
Receive
IR Pulse
(RX pin)
Character
Data Bits
Sta
rt
Stop
00
0
11
1
TX Data
Transmit
IR Pulse
(TX Pin)
Bit Time
1/2 Bit Time
3/16 Bit Time
IrEncoder-1
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| ST16C654DCQ64-F | IC UART FIFO 64B QUAD 64LQFP |
| ST16C654IQ100-F | IC UART FIFO 64B QUAD 100QFP |
| XR16V654IL-F | IC UART FIFO 64B QUAD 48QFN |
| XR16C2850CM-F | IC UART FIFO 128B DUAL 48TQFP |
| ST16C554DIQ64-F | IC UART FIFO 16B QUAD 64LQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ST16C654CQ64TR-F | 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 QUAD UARTW/64BYTE FIFO RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel |
| ST16C654D | 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO |
| ST16C654DCQ64 | 鍒堕€犲晢:Exar Corporation 鍔熻兘鎻忚堪: |
| ST16C654DCQ64-0A-EB | 鍔熻兘鎻忚堪:鐣岄潰闁嬬櫦(f膩)宸ュ叿 Supports C654D 64 ld TQFP, ISA Interface RoHS:鍚� 鍒堕€犲晢:Bourns 鐢�(ch菐n)鍝�:Evaluation Boards 椤炲瀷:RS-485 宸ュ叿鐢ㄤ簬瑭曚及:ADM3485E 鎺ュ彛椤炲瀷:RS-485 宸ヤ綔闆绘簮闆诲:3.3 V |
| ST16C654DCQ64-F | 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 QUAD UARTW/64BYTE FIFO RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel |
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