參數(shù)資料
型號(hào): ST16C650ACP40
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 2.90V TO 5.5V UART WITH 32-BYTE FIFO
中文描述: 1 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PDIP40
封裝: 0.600 INCH, PLASTIC, DIP-40
文件頁(yè)數(shù): 14/53頁(yè)
文件大?。?/td> 666K
代理商: ST16C650ACP40
ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
á
REV. 5.0.0
14
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate.
Table 4
shows the standard data rates available with a 14.7456 MHz crystal or external
clock at 16X clock rate. When using a non-standard data rate crystal or external clock, the divisor value can be
calculated for DLL/DLM with the following equation.
2.9
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 32 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
Transmitter
F
IGURE
8. B
AUD
R
ATE
G
ENERATOR
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
T
ABLE
4: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
O
UTPUT
Data Rate
MCR Bit-7=1
O
UTPUT
Data Rate
MCR Bit-7=0
D
IVISOR
FOR
16x
Clock (Decimal)
D
IVISOR
FOR
16x
Clock (HEX)
DLM
P
ROGRAM
V
ALUE
(HEX)
DLL
P
ROGRAM
V
ALUE
(HEX)
D
ATA
R
ATE
E
RROR
(%)
100
400
2304
900
09
00
0
600
2400
384
180
01
80
0
1200
4800
192
C0
00
C0
0
2400
9600
96
60
00
60
0
4800
19.2k
48
30
00
30
0
9600
38.4k
24
18
00
18
0
19.2k
76.8k
12
0C
00
0C
0
38.4k
153.6k
6
06
00
06
0
57.6k
230.4k
4
04
00
04
0
115.2k
460.8k
2
02
00
02
0
230.4k
921.6k
1
01
00
01
0
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL and DLM
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X
Sampling
Rate Clock to
Transmitter
Baud Rate
Generator
Logic
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