REV. 5.0.3 2.90V TO 5.5V UART WITH 32-BYTE FIFO XFR [4]: Xon-Any Enable This bit enables and disables the Xon-Any function when Xo" />
參數(shù)資料
型號(hào)： ST16C650ACJ44-F
廠商： Exar Corporation
文件頁數(shù)： 27/50頁
文件大?。?/td> 0K
描述： IC UART FIFO 32B 44PLCC
標(biāo)準(zhǔn)包裝： 27
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 32 字節(jié)
規(guī)程： 打印機(jī)，RS232，RS422，RS485
電源電壓： 2.9 V ~ 5.5 V
帶并行端口： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 管件
其它名稱： 1016-1663
ST16C650ACJ44-F-ND
ST16C650A
33
REV. 5.0.3
2.90V TO 5.5V UART WITH 32-BYTE FIFO
XFR [4]: Xon-Any Enable
This bit enables and disables the Xon-Any function when Xon/Xoff software flow control is enabled.
Logic 0 = Disable the Xon-Any function.
Logic 1 = Enable the Xon-Any function. The receiver will use any received character as an Xon character
and resume data transmission.
XFR [5]: Invert Auto RS-485 Control Output
When Auto RS485 feature is enabled, XFR[2]=1, RTS# output automatically changes its logic state to control
the RS-485 transceiver.
Logic 0 = During auto RS-485, RTS# control output signal to the transceiver is logic 1 for transmit and logic 0
for receive.
Logic 1 = The RTS# output control signal to the transceiver is logic 0 for transmit and logic 1 for receive. User
must assert RTS# for operation to take effect.
XFR [7:6]: Reserved
4.10
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register are used to indicate the changed information. These bits
are set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general
purpose inputs/outputs when they are not used with modem signals.
MSR[0]: Delta CTS# Input Flag
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
Logic 0 = No change on RI# input (default).
Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
Logic 0 = No change on CD# input (default).
Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the
modem CTS# signal. A logic 1 on the CTS# pin will stop UART transmitter as soon as the current character
has finished transmission, and a logic 0 will resume data transmission. Normally MSR bit-4 bit is the
compliment of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR
register. The CTS# input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
DSR# (active high, logical 1). Normally this bit is the compliment of the DSR# input. In the loopback mode, this
bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input
when the modem interface is not used.
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