參數(shù)資料
型號(hào)： ST16C580
廠商： Exar Corporation
英文描述： UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER
中文描述： UART的16字節(jié)FIFO的和紅外線(xiàn)（IrDA）編碼/解碼器
文件頁(yè)數(shù)： 21/41頁(yè)
文件大?。?/td> 244K
代理商： ST16C580
ST16C580
21
Rev. 1.20
Table 6, INTERRUPT SOURCE TABLE
Priority
Level
[ ISR BITS ]
Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Source of the interrupt
1
2
2
3
4
5
6
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time out)
TXRDY ( Transmitter Holding Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xoff signal)/ Special character
CTS, RTS change of state
ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
ISR BIT 1-3: (logic 0 or cleared s the default condition)
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, and 3 (See Interrupt
Source Table).
ISR BIT 4-5: (logic 0 or cleared s the default condition)
These bits are enabled when EFR bit-4 is set to a logic
1. ISR bit-4 indicates that matching Xoff character(s)
have been detected. ISR bit-5 indicates that CTS,
RTS have been generated. Note that once set to a
logic 1, the ISR bit-4 will stay a logic 1 until Xon
character(s) are received.
ISR BIT 6-7: (logic 0 or cleared s the default condition)
These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFO’s
are enabled
Line Control Register (LCR)
The Line Control Register is used to specify the
asynchronous data communication format. The word
length, the number of stop bits, and the parity are
selected by writing the appropriate bits in this register.
LCR BIT 0-1: (logic 0 or cleared s he default condition)
These two bits specify the word length to be transmitted
or received.
BIT-1
BIT-0
Word length
0
0
1
1
0
1
0
1
5
6
7
8
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in
conjunction with the programmed word length.
BIT-2
Word length
Stop bit
length
(Bit time(s))
0
1
1
5,6,7,8
5
6,7,8
1
1-1/2
2
LCR BIT-3:
Parity or no parity can be selected via this bit.
Logic 0 = No parity (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, receiver checks the data and parity for transmis-
sion errors.
相關(guān)PDF資料
PDF描述
ST16C580CQ48 UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER
ST16C580IJ44 UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER
ST16C580IP40 UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER
ST16C580IQ48 UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER
ST16C580CP40 Linear Voltage Regulator IC; Output Current Max:350mA; Supply Voltage Max:6V; Package/Case:8-TSSOP; Output Current:350mA; Output Voltage:3.3V; Current Rating:30.05A; Leaded Process Compatible:No; Output Voltage Max:3.3V
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST16C580_05 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER
ST16C580CJ44 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER
ST16C580CP40 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER
ST16C580CQ-0A-EVB 功能描述:界面開(kāi)發(fā)工具 Supports C580 48 ld TQFP, ISA Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
ST16C580CQ48 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*