參數(shù)資料
型號(hào)： ST16C554D
廠商： Exar Corporation
英文描述： Quad UART with 16-Byte FIFO(四通用異步接收器/發(fā)送器（帶16字節(jié)的先進(jìn)先出）)
中文描述： 四路的UART具有16字節(jié)FIFO（四通用異步接收器/發(fā)送器（帶16字節(jié)的先進(jìn)先出））
文件頁(yè)數(shù)： 22/40頁(yè)
文件大?。?/td> 506K
代理商： ST16C554D
ST16C554/554D/68C554
22
Rev. 3.10
LCR
Bit-5
LCR
Bit-4
LCR
Bit-3
Parity selection
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
No parity
Odd parity
Even parity
Force parity 1
Forced parity 0
LCR BIT-6:
When enabled the Break control bit causes a break
condition to be transmitted (the TX output is forced to
a logic 0 state). This condition exists until disabled by
setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition. (normal default
condition)
Logic 1 = Forces the transmitter output (TX) to a logic
0 for alerting the remote receiver to a line break
condition.
LCR BIT-7:
Not used - Initialized to a logic 0.
Modem Control Register (MCR)
This register controls the interface with the modem or
a peripheral device.
MCR BIT-0:
Logic 0 = Force -DTR output to a logic 1. (normal
default condition)
Logic 1 = Force -DTR output to a logic 0.
MCR BIT-1:
Logic 0 = Force -RTS output to a logic 1. (normal
default condition)
Logic 1 = Force -RTS output to a logic 0.
MCR BIT-2:
This bit is used in the Loopback mode only. In the
loopback mode this bit is use to write the state of the
modem -RI interface signal via -OP1.
MCR BIT-3: (
Used to control the modem -CD signal
in the loopback mode.)
Logic 0 = Forces INT (A-D) outputs to the three state
mode during the 16 mode. (normal default condition)
In the Loopback mode, sets -OP2 (-CD) internally to a
logic 1.
Logic 1 = Forces the INT (A-D) outputs to the active
mode during the 16 mode. In the Loopback mode, sets
-OP2 (-CD) internally to a logic 0.
MCR BIT-4:
Logic 0 = Disable loopback mode. (normal default
condition)
Logic 1 = Enable local loopback mode (diagnostics).
MCR BIT 5-7:
Not used - Initialized to a logic 0.
Line Status Register (LSR)
This register provides the status of data transfers
between. the 554D and the CPU.
LSR BIT-0:
Logic 0 = No data in receive holding register or FIFO.
(normal default condition)
Logic 1 = Data has been received and is saved in the
receive holding register or FIFO.
LSR BIT-1:
Logic 0 = No overrun error. (normal default condition)
Logic 1 = Overrun error. A data overrun error occurred
in the receive shift register. This happens when addi-
tional data arrives while the FIFO is full. In this case
the previous data in the shift register is overwritten.
Note that under this condition the data byte in the
receive shift register is not transfered into the FIFO,
therefore the data in the FIFO is not corrupted by the
error.
LSR BIT-2:
Logic 0 = No parity error. (normal default condition)
Logic 1 = Parity error. The receive character does not
have correct parity information and is suspect. In the
FIFO mode, this error is associated with the character
at the top of the FIFO.
LSR BIT-3:
Logic 0 = No framing error. (normal default condition)
Logic 1 = Framing error. The receive character did not
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST16C554DCJ 制造商:Exar Corporation 功能描述:
ST16C554DCJ68 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: 制造商:Exar Corporation 功能描述:IC,UART,LDCC,68PIN,PLASTIC
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ST16C554DCJ68TR 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:
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