參數(shù)資料
型號(hào)： ST16C554CQ64
廠(chǎng)商： EXAR CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： Linear Voltage Regulator IC; Output Current Max:350mA; Supply Voltage Max:6V; Package/Case:8-TSSOP; Current Rating:350mA; Leaded Process Compatible:No; Output Voltage Max:2.8V; Peak Reflow Compatible (260 C):No
中文描述： 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64
文件頁(yè)數(shù)： 20/40頁(yè)
文件大?。?/td> 518K
代理商： ST16C554CQ64
ST16C554/554D/68C554
20
Rev. 3.10
Transmit operation in mode 1:
When the 554D is in FIFO mode ( FCR bit-0 = logic 1,
FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1
when the transmit FIFO is completely full. It will be a
logic 0 if one or more FIFO locations are empty.
Receive operation in mode 1:
When the 554D is in FIFO mode (FCR bit-0 = logic 1,
FCR bit-3 = logic 1) and the trigger level has been
reached, or a Receive Time Out has occurred, the -
RXRDY pin will go to a logic 0. Once activated, it will
go to a logic 1 after there are no more characters in the
FIFO.
FCR BIT 4-5:
Not used - Initialized to a logic 0.
FCR BIT 6-7: (logic 0 or cleared is the default condi-
tion, Rx trigger level = 1)
These bits are used to set the trigger level for the
receive FIFO interrupt.
An interrupt is generated when the number of charac-
ters in the FIFO equals the programmed trigger level.
However the FIFO will continue to be loaded until it is
full.
BIT-7
BIT-6
RX FIFO trigger level
0
0
1
1
0
1
0
1
1
4
8
14
Interrupt Status Register (ISR)
The 554D provides four levels of prioritized interrupts
to minimize external software interaction. The Inter-
rupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the
ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are
acknowledged until the pending interrupt is serviced.
Whenever the interrupt status register is read, the
interrupt status is cleared. However it should be noted
that only the current pending interrupt is cleared by the
read. A lower level interrupt may be seen after reread-
ing the interrupt status bits. The Interrupt Source
Table 7 (below) shows the data values (bit 0-5) for the
four prioritized interrupt levels and the interrupt
sources associated with each of these interrupt levels:
Table 7, INTERRUPT SOURCE TABLE
Priority
Level
[ ISR BITS ]
Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Source of the interrupt
1
2
2
3
4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time out)
TXRDY ( Transmitter Holding Register Empty)
MSR (Modem Status Register)
相關(guān)PDF資料
PDF描述
ST16C554DCQ64 QUAD UART WITH 16-BYTE FIFOS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST16C554CQ64-F 功能描述:UART 接口集成電路 2.97V-5.5V 16B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
ST16C554D 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:QUAD UART WITH 16-BYTE FIFOS
ST16C554DCJ 制造商:Exar Corporation 功能描述:
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ST16C554DCJ-68 制造商:Exar Corporation 功能描述:IC,UART,LDCC,68PIN,PLASTIC
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