參數(shù)資料
型號(hào): ST16C550IQ48-F
廠商: Exar Corporation
文件頁(yè)數(shù): 8/35頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO 16B SGL 48TQFP
標(biāo)準(zhǔn)包裝: 250
特點(diǎn): *
通道數(shù): 1,UART
FIFO's: 16 字節(jié)
電源電壓: 2.97 V ~ 5.5 V
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤(pán)
其它名稱: 1016-1262
ST16C550
16
Rev. 5.01
Interrupt Status Register (ISR)
The ST16C550 provides four levels of prioritized inter-
rupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR
will provide the user with the highest pending interrupt
level to be serviced. No other interrupts are acknowl-
edged until the pending interrupt is serviced. Whenever
the interrupt status register is read, the interrupt status
is cleared. However it should be noted that only the
current pending interrupt is cleared by the read. A lower
level interrupt may be seen after rereading the interrupt
status bits. The Interrupt Source Table 5 (below) shows
the data values (bit 0-3) for the four prioritized interrupt
levels and the interrupt sources associated with each
of these interrupt levels:
Table 5, INTERRUPT SOURCE TABLE
Priority
[ISR]
Level
Bit-3 Bit-2 Bit-1 Bit-0
Source of the interrupt
X
0001
No interrupt pending
1
0110
LSR (Receiver Line Status Register)
2
0100
RXRDY (Received Data Ready)
2
1100
RXRDY (Receive Data time out)
3
0010
TXRDY ( Transmitter Holding Register Empty)
4
0000
MSR (Modem Status Register)
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