參數(shù)資料
型號(hào): ST16C550CQ48
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: UART WITH 16-BYTE FIFO’s
中文描述: 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP48
封裝: TQFP-48
文件頁數(shù): 9/35頁
文件大小: 227K
代理商: ST16C550CQ48
ST16C550
9
Rev. 4.30
Table 2, INTERNAL REGISTER DECODE
A2
A1
A0
READ MODE
WRITE MODE
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR):
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Receive Holding Register
Interrupt Enable Register
Interrupt Status Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
Reserved
Reserved
Scratchpad Register
Baud Rate Generator Registers (DLL/DLM). Accessible only when LCR bit-7 is set to 1.
0
0
0
0
0
1
LSB of Divisor Latch
MSB of Divisor Latch
LSB of Divisor Latch
MSB of Divisor Latch
FIFO Operation
The 16 byte transmit and receive data FIFO’s are
enabled by the FIFO Control Register (FCR) bit-0.
With 16C550 devices, the user can set the receive
trigger level but not the transmit trigger level. The
receiver FIFO section includes a time-out function to
ensure data is delivered to the external CPU. An
interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the load-
ing of a character or the receive trigger level has not
been reached.
Time-out Interrupts
When two interrupt conditions have the same priority,
it is important to service these interrupts correctly.
Receive Data Ready and Receive Time Out have the
same interrupt priority (when enabled by IER bit-0).
The receiver issues an interrupt after the number of
characters have reached the programmed trigger level.
In this case the ST16C550 FIFO may hold more char-
acters than the programmed trigger level. Following the
removal of a data byte, the user should recheck LSR bit-
0 for additional characters. A Receive Time Out will not
occur if the receive FIFO is empty. The time out counter
is reset at the center of each stop bit received or each
time the receive holding register (RHR) is read (see
Figure 10, Receive Time-out Interrupt). The actual time
out value is T (
T
ime out length in bits) = 4 X P
(
P
rogrammed word length) + 12. To convert the time out
value to a character value, the user has to consider the
complete word length, including data information
length, start bit, parity bit, and the size of stop bit, i.e.,
1X, 1.5X, or 2X bit times.
Example -A: If the user programs a word length of 7,
with no parity and one stop bit, the time out will be:
T = 4 X 7( programmed word length) +12 = 40 bit times.
The character time will be equal to 40 / 9 = 4.4
characters, or as shown in the fully worked out example:
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