參數(shù)資料
型號: ST16C454IJ68
廠商: STARTECH SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: QUAD UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)
中文描述: 4 CHANNEL(S), 448K bps, SERIAL COMM CONTROLLER, PQCC68
文件頁數(shù): 12/30頁
文件大?。?/td> 378K
代理商: ST16C454IJ68
ST16C454/68C454
12
Rev. 3.20
Loop-back Mode
The internal loop-back capability allows onboard diag-
nostics. In the loop-back mode the normal modem
interface pins are disconnected and reconfigured for
loop-back internally. MCR register bits 0-3 are used
for controlling loop-back diagnostic testing. In the
loop-back mode OP1 and OP2 in the MCR register
(bits 3/2) control the modem -RI and -CD inputs
respectively. MCR signals -DTR and -RTS (bits 0-1)
are used to control the modem -CTS and -DSR inputs
respectively. The transmitter output (TX) and the
receiver input (RX) are disconnected from their asso-
ciated interface pins, and instead are connected to-
gether internally (See Figure 12). The -CTS, -DSR, -
CD, and -RI are disconnected from their normal
modem control inputs pins, and instead are connected
internally to -DTR, -RTS, -OP1 and -OP2. Loop-back
test data is entered into the transmit holding register
via the user data bus interface, D0-D7. The transmit
UART serializes the data and passes the serial data to
the receive UART via the internal loop-back connec-
tion. The receive UART converts the serial data back
into parallel data that is then made available at the
user data interface, D0-D7. The user optionally com-
pares the received data to the initial transmitted data
for verifying error free operation of the UART TX/RX
circuits.
In this mode, the receiver and transmitter interrupts
are fully operational. The Modem Control Interrupts
are also operational. However, the interrupts can only
be read using lower four bits of the Modem Control
Register (MCR bits 0-3) instead of the four Modem
Status Register bits 4-7. The interrupts are still con-
trolled by the IER.
C1
22pF
C2
33pF
X1
1.8432 MHz
X
X
Figure 8, Crystal oscillator connection
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