參數(shù)資料
型號(hào)： ST16C450IQ48
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)
中文描述： 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP48
封裝： TQFP-48
文件頁(yè)數(shù)： 13/28頁(yè)
文件大?。?/td> 182K
代理商： ST16C450IQ48
ST16C450
13
Rev. 4.20
Transmit and Receive Holding Register
The serial transmitter section consists of an 8-bit
Transmit Hold Register (THR) and Transmit Shift
Register (TSR). The status of the THR is provided in
the Line Status Register (LSR). Writing to the THR
transfers the contents of the data bus (D7-D0) to the
THR, providing that the THR or TSR is empty. The
THR empty flag in the LSR register will be set to a logic
1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can
be performed when the transmit holding register
empty flag is set.
The serial receive section also contains an 8-bit
Receive Holding Register, RHR. Receive data is
removed from the ST16C450 and receive by reading
the RHR register. The receive section provides a
mechanism to prevent false starts. On the falling edge
of a start or false start bit, an internal receiver counter
starts counting clocks at 16x clock rate. After 7 1/2
clocks the start bit time should be shifted to the center
of the start bit. At this time the start bit is sampled and
if it is still a logic 0 it is validated. Evaluating the start
bit in this manner prevents the receiver from assem-
bling a false character. Receiver status codes will be
posted in the LSR.
Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the inter-
rupts from receiver ready, transmitter empty, line
status and modem status registers. These interrupts
would normally be seen on the ST16C450 INT output
pin.
IER BIT-0:
Logic 0 = Disable the receiver ready interrupt. (normal
default condition)
Logic 1 = Enable the receiver ready interrupt.
IER BIT-1:
Logic 0 = Disable the transmitter empty interrupt.
(normal default condition)
Logic 1 = Enable the transmitter empty interrupt.
IER BIT-2:
Logic 0 = Disable the receiver line status interrupt.
(normal default condition)
Logic 1 = Enable the receiver line status interrupt.
IER BIT-3:
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
IER BIT 4-7:Not used and set to “0”.
Interrupt Status Register (ISR)
The ST16C450 provides four levels of prioritized
interrupts to minimize external software interaction.
The Interrupt Status Register (ISR) provides the user
with four interrupt status bits. Performing a read cycle
on the ISR will provide the user with the highest
pending interrupt level to be serviced. No other inter-
rupts are acknowledged until the pending interrupt is
serviced. Whenever the interrupt status register is
read, the interrupt status is cleared. However it should
be noted that only the current pending interrupt is
cleared by the read. A lower level interrupt may be seen
after rereading the interrupt status bits. The Interrupt
Source Table 5 (below) shows the data values (bit 0-3)
for the four prioritized interrupt levels and the interrupt
sources associated with each of these interrupt levels:
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST16C450IQ48-F 功能描述:UART 接口集成電路 SINGLE UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
ST16C450IQ48TR-F 制造商:Exar Corporation 功能描述:UART 1-CH 1Byte FIFO 3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:ST16C450 Series 1.5 Mbps 5.5 V Universal Asynchronous UART - TQFP-48 制造商:Exar Corporation 功能描述:ST16C450IQ48TR-F
ST16C452 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH PARALLEL PRINTER PORT
ST16C452CJ68 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:UART 2-CH 3.3V/5V 68-Pin PLCC
ST16C452CJ68-F 功能描述:UART 接口集成電路 DUAL UART W/PARALEL PRINTER PORT RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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