REV. 4.2.2 2.12 Internal Loopback The 2552 UART provides an internal loopb" />
參數(shù)資料
型號: ST16C2552IJ44-F
廠商: Exar Corporation
文件頁數(shù): 6/34頁
文件大?。?/td> 0K
描述: IC UART FIFO 16B DUAL 44PLCC
標準包裝: 27
特點: *
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 3.3 V ~ 5 V
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應商設備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
其它名稱: 1016-1258-5
ST16C2552
14
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
REV. 4.2.2
2.12
Internal Loopback
The 2552 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 11 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 11. INTERNAL LOOP BACK IN CHANNEL A AND B
TXA/TXB
RXA/RXB
M
o
dem
/
Gen
e
ral
Purpo
s
e
Contro
lL
ogi
c
In
ternal
D
a
ta
Bus
Lines
and
C
o
ntr
o
lSigna
ls
RTSA#/RTSB#
MCR bit-4=1
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTSA#/CTSB
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
(OP2A#/OP2B#)
VCC
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