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參數(shù)資料
| 型號(hào)： | ST16C2550CQ48 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFO’S |
| 中文描述： | 2 CHANNEL(S), 4M bps, SERIAL COMM CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, TQFP-48 |
| 文件頁數(shù)： | 16/34頁 |
| 文件大小： | 443K |
| 代理商： | ST16C2550CQ48 |
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ST16C2550
16
Rev. 3.20
E) LSR BIT-7 will show if any FIFO data errors
occurred.
IER BIT-0:
In the 16C450 mode, This interrupt will be issued when
the RHR has data or is cleared when the RHR is
empty. In the FIFO mode, this interrupt will be issued
when the FIFO has reached the programmed trigger
level or is cleared when the FIFO drops below the
trigger level.
Logic 0 = Disable the receiver ready (ISR level 2,
RXRDY) interrupt. (normal default condition)
Logic 1 = Enable the RXRDY (ISR level 2) interrupt.
IER BIT-1:
In the 16C450 mode, this interrupt will be issued
whenever the THR is empty and is associated with bit-
5 in the LSR register. In the FIFO modes, this interrupt
will be issued whenever the FIFO and THR are empty
Logic 0 = Disable the Transmit Holding Register
Empty (TXRDY) interrupt. (normal default condition)
Logic 1 = Enable the TXRDY (ISR level 3) interrupt.
IER BIT-2:
This interrupt will be issued whenever an receive data
error condition exists as reflected in LSR bits 1-4.
Logic 0 = Disable the receiver line status interrupt.
(normal default condition)
Logic 1 = Enable the receiver line status interrupt.
IER BIT-3:
This interrupt will be issued whenever there is a
modem status change as reflected in MSR bits 0-3.
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
IER BIT 4-7:
Not Used - initialized to a logic 0.
FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the
FIFOs, set the receive FIFO trigger levels, and select
the DMA mode. The DMA, and FIFO modes are
defined as follows:
DMA MODE
Mode 0
single transmit or receive operation, and is similar to
the ST16C450 mode. Transmit Ready (-TXRDY) on
44/48 pin packages will go to a logic 0 when ever an
empty transmit space is available in the Transmit
Holding Register (THR). Receive Ready (-RXRDY) on
44,/48 pin packages will go to a logic 0 whenever the
Receive Holding Register (RHR) is loaded with a
character.
Mode 1
Set and enable the interrupt in a block
mode operation. The transmit interrupt is set when the
transmit FIFO is below the programmed trigger level.
-TXRDY on 44/48 pin packages remains a logic 0 as
long as one empty FIFO location is available. The
receive interrupt is set when the receive FIFO fills to
the programmed trigger level. However the FIFO
continues to fill regardless of the programmed level
until the FIFO is full. -RXRDY on 44/48 pin packages
remains a logic 0 as long as the FIFO fill level is above
the programmed trigger level.
Set and enable the interrupt for each
FCR BIT-0:
Logic 0 = Disable the transmit and receive FIFO.
(normal default condition)
Logic 1 = Enable the transmit and receive FIFO. This
bit must be a 1 when other FCR bits are written to or
they will not be programmed.
FCR BIT-1:
Logic 0 = No FIFO receive reset. (normal default
condition)
Logic 1 = Clears the contents of the receive FIFO and
resets the FIFO counter logic (the receive shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
FCR BIT-2:
Logic 0 = No FIFO transmit reset. (normal default
condition)
Logic 1 = Clears the contents of the transmit FIFO and
resets the FIFO counter logic (the transmit shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
相關(guān)PDF資料 |
PDF描述 |
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| ST16C2550IJ44 | DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFO’S |
| ST16C2550IP40 | DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFO’S |
| ST16C2550CJ44 | DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFO’S |
| ST16C2550CP40 | Power Supply IC; Supply Voltage Max:6V; Output Voltage:1.3V; Package/Case:20-TSSOP; Leaded Process Compatible:No; Output Voltage Max:1.3V; Peak Reflow Compatible (260 C):No; Supply Voltage Min:2.7V; Mounting Type:Surface Mount |
| ST16C2550IQ48 | DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFO’S |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C2550CQ48-F | 功能描述:UART 接口集成電路 2.97V-5.5V 16B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2550CQ48TR-F | 功能描述:UART 接口集成電路 DUAL UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2550IJ44 | 制造商:Exar Corporation 功能描述: |
| ST16C2550IJ44-F | 功能描述:UART 接口集成電路 DUAL UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2550IJ44TR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 16Byte FIFO 3.3V/5V 44-Pin PLCC T/R 制造商:Exar Corporation 功能描述:ST16C2550IJ44TR-F |
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