REV. 4.4.1 NOTE: Pin type: " />
參數(shù)資料
型號(hào)： ST16C2550CJ44TR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 34/37頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 16B DUAL 44PLCC
標(biāo)準(zhǔn)包裝： 500
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 16 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.97 V ~ 5.5 V
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
ST16C2550
6
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 4.4.1
NOTE: Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
CTSB#
25
28
23
I
UART channel B Clear-to-Send (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
DTRB#
34
38
35
O
UART channel B Data-Terminal-Ready (active low) or
general purpose output. If it is not used, leave it uncon-
nected.
DSRB#
22
25
20
I
UART channel B Data-Set-Ready (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
CDB#
19
21
16
I
UART channel B Carrier-Detect (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
RIB#
23
26
21
I
UART channel B Ring-Indicator (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
OP2B#
13
15
9
O
Output Port 2 Channel B - The output state is defined by
the user and through the software setting of MCR[3].
INTB is set to the active mode and OP2B# output to a
logic 0 when MCR[3] is set to a logic 1. INTB is set to the
three state mode and OP2B# to a logic 1 when MCR[3] is
set to a logic 0. See MCR[3]. This output should not be
used as a general output else it will disturb the INTB out-
put functionality. If it is not used, leave it unconnected.
ANCILLARY SIGNALS
XTAL1
16
18
13
I
Crystal or external clock input.
XTAL2
17
19
14
O
Crystal or buffered clock output.
RESET
35
39
36
I
Reset (active high) - A longer than 40 ns logic 1 pulse on
this pin will reset the internal registers and all outputs.
The UART transmitter output will be held at logic 1, the
receiver input will be ignored and outputs are reset during
reset period (see External Reset Conditions).
VCC
40
44
42
Pwr
2.97V to 5.5V power supply. All inputs are 5V tolerant for
devices with top marking of "A2 YYWW" and newer.
GND
20
22
17
Pwr
Power supply common, ground.
N.C.
-
12, 24, 25,
37
No Connection. These pins are open, but typically, should
be connected to GND for good design practice.
Pin Description
NAME
40-PDIP
PIN #
44-PLCC
PIN #
48-TQFP
PIN #
TYPE
DESCRIPTION
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