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參數(shù)資料
| 型號： | ST16C2450IQ48-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 23/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO DUAL 48TQFP |
| 標準包裝： | 250 |
| 特點： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 1 字節(jié) |
| 規(guī)程： | RS232 |
| 電源電壓： | 2.97 V ~ 5.5 V |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1670 ST16C2450IQ48-F-ND |
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xr
ST16C2450
REV. 4.0.1
2.97V TO 5.5V DUART
3
PIN DESCRIPTIONS
Pin Description
NAME
44-PLCC
PIN #
48-TQFP
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
29
30
31
26
27
28
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
9
8
7
6
5
4
3
2
3
2
1
48
47
46
45
44
IO
Data bus lines [7:0] (bidirectional).
IOR#
24
19
I
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
IOW#
20
15
I
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
CSA#
16
10
I
UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
CSB#
17
11
I
UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
INTA
33
30
O
UART channel A Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTA is set to the
active mode and OP2A# output to a logic 0 when MCR[3] is set to a
logic 1. INTA is set to the three state mode and OP2A# to a logic 1
when MCR[3] is set to a logic 0 (default).
INTB
32
29
O
UART channel B Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTB is set to the
active mode and OP2B# output to a logic 0 when MCR[3] is set to a
logic 1. INTB is set to the three state mode and OP2B# to a logic 1
when MCR[3] is set to a logic 0 (default).
MODEM OR SERIAL I/O INTERFACE
TXA
13
7
O
UART channel A Transmit Data. If it is not used, leave it unconnected.
RXA
11
5
I
UART channel A Receive Data. Normal receive data input must idle at
logic 1 condition. If it is not used, tie it to VCC or pull it high via a 100k
ohm resistor.
RTSA#
36
33
O
UART channel A Request-to-Send (active low) or general purpose out-
put. If it is not used, leave it unconnected.
CTSA#
40
38
I
UART channel A Clear-to-Send (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C2450IQ48TR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 1Byte FIFO 3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:ST16C2450IQ48TR-F |
| ST16C2451 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUART |
| ST16C2550 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUART WITH 16-BYTE FIFO |
| ST16C2550_04 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUART WITH 16-BYTE FIFO |
| ST16C2550CJ-0A-EB | 功能描述:界面開發(fā)工具 Supports C2550 44 ld PLCC, ISA Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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