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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | ST16C2450CJ44-F |
| 寤犲晢锛� | Exar Corporation |
| 鏂囦欢闋佹暩(sh霉)锛� | 26/30闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DUART 44PLCC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 27 |
| 鐗归粸(di菐n)锛� | * |
| 閫氶亾鏁�(sh霉)锛� | 2锛孌UART |
| FIFO's锛� | 1 瀛楃瘈(ji茅) |
| 瑕�(gu墨)绋嬶細 | RS232 |
| 闆绘簮闆诲锛� | 2.97 V ~ 5.5 V |
| 甯舵晠闅滃暉鍕�(d貌ng)浣嶆娓姛鑳斤細 | 鏄� |
| 甯惰(di脿o)鍒惰В瑾�(di脿o)鍣ㄦ帶鍒跺姛鑳斤細 | 鏄� |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 44-LCC锛圝 褰㈠紩绶氾級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 44-PLCC锛�16.59x16.59锛� |
| 鍖呰锛� | 绠′欢 |
| 鍏跺畠鍚嶇ū锛� | 1016-1253 |
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ST16C2450
REV. 4.0.1
2.97V TO 5.5V DUART
5
Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
1.0 PRODUCT DESCRIPTION
The ST16C2450 (2450) integrates the functions of two 16C450 Universal Asynchrounous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The 2450 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-
parallel data conversions for both the transmitter and receiver sections. These functions are necessary for
converting the serial data stream into parallel data that is required with digital data systems. Synchronization
for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to
provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip.
The 2450 represents such an integration with greatly enhanced features. The 2450 is fabricated with an
advanced CMOS process. The 2450 is capable of operation up to 1.5 Mbps with a 24 MHz clock. With a crystal
or external clock input of 14.7456 MHz the user can select data rates up to 921.6 Kbps.
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 2450 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C450 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in Figure 3.
ANCILLARY SIGNALS
XTAL1
18
13
I
Crystal or external clock input.
XTAL2
19
14
O
Crystal or buffered clock output.
RESET
39
36
I
Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will
reset the internal registers and all outputs. The UART transmitter output
will be held at logic 1, the receiver input will be ignored and outputs are
reset during reset period.
VCC
44
42
Pwr
2.97V to 5.5V power supply. All inputs are 5V tolerant for devices with
top marking of "A2 YYWW" and newer.
GND
22
17
Pwr
Power supply common, ground.
N.C.
1, 12, 23,
34
6, 12, 18,
24, 25, 31,
37, 43
-
No Connection. These pins are open, but typically, should be con-
nected to GND for good design practice.
Pin Description
NAME
44-PLCC
PIN #
48-TQFP
PIN #
TYPE
DESCRIPTION
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| ST16C2550CJ44-F | IC DUART FIFO 16B 44PLCC |
| ST16C2552IJ44TR-F | IC UART FIFO 16B DUAL 44PLCC |
| ST16C450CJ44-F | IC UART SINGLE 44PLCC |
| ST16C450CP40-F | IC INTERFACE UART |
| ST16C452IJ68-F | IC UART W/PAR PORT DUAL 68PLCC |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ST16C2450CJ44TR | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪: 鍒堕€犲晢:Exar Corporation 鍔熻兘鎻忚堪: |
| ST16C2450CJ44TR-F | 鍒堕€犲晢:Exar Corporation 鍔熻兘鎻忚堪:UART 2-CH 1Byte FIFO 3.3V/5V 44-Pin PLCC T/R 鍒堕€犲晢:Exar Corporation 鍔熻兘鎻忚堪:ST16C2450CJ44TR-F |
| ST16C2450CP40 | 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 DUAL UART RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel |
| ST16C2450CP40-F | 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 DUAL UART RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel |
| ST16C2450CQ-0A-EB | 鍔熻兘鎻忚堪:鐣岄潰闁嬬櫦(f膩)宸ュ叿 Supports C2450 48 ld TQFP, ISA Interface RoHS:鍚� 鍒堕€犲晢:Bourns 鐢�(ch菐n)鍝�:Evaluation Boards 椤炲瀷:RS-485 宸ュ叿鐢ㄤ簬瑭�(p铆ng)浼�:ADM3485E 鎺ュ彛椤炲瀷:RS-485 宸ヤ綔闆绘簮闆诲:3.3 V |
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