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參數(shù)資料
| 型號： | ST16C1451IQ48 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2.97V TO 5.5V UART |
| 中文描述： | 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, TQFP-48 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大小： | 355K |
| 代理商： | ST16C1451IQ48 |
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REV. 4.2.0
ST16C1450/51
2.97V TO 5.5V UART
15
4.0
INTERNAL REGISTER DESCRIPTIONS
4.1
See “Receiver” on page 10.
4.2
Transmit Holding Register (THR) - Write-Only
See “Transmitter” on page 9.
4.3
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character.
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR is empty. If the THR is empty
when this bit is enabled, an interrupt will be generated. Note that this interrupt does not behave in the same
manner as the industry standard 16C550.
See “Interrupt Clearing:” on page 16.
Logic 0 = Disable Transmit Ready interrupt (default).
Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in the RHR.
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
IER[4]: Reserved
IER[5]: Special Mode Enable
Logic 0 = Disable special mode functions (default).
Logic 1 = Enable special mode functions in addition to basic ST16C1450 functions. Enables ISR bits 4-5
(TXRDY/RXRDY), MCR bit-2 (soft reset) and MCR bit-7 (power down) functions.
IER[7:6]: Reserved
4.4
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,
Table 4
, shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
Receive Holding Register (RHR) - Read- Only
相關PDF資料 |
PDF描述 |
|---|---|
| ST16C1451 | 2.97V TO 5.5V UART |
| ST16C1550 | 2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C1550CJ28 | 2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C1550CP28 | 2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C1550CQ48 | 2.97V TO 5.5V UART WITH 16-BYTE FIFO |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C1550 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C1550_05 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C1550CJ28 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| ST16C1550CJ28-F | 功能描述:UART 接口集成電路 UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C1550CJ28-F | 制造商:Exar Corporation 功能描述:IC SGL UART 1.5MBPS 5.5V 28-PLCC |
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