參數(shù)資料
型號: ST16C1451IP28
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 2.97V TO 5.5V UART
中文描述: 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 8/32頁
文件大?。?/td> 355K
代理商: ST16C1451IP28
ST16C1450/51
2.97V TO 5.5V UART
á
REV. 4.2.0
8
2.2
The 145X includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to
the Baud Rate Generators (BRG) in the UART. XTAL1 is the input to the oscillator or external clock buffer input
with XTAL2 pin being the output. For programming details, see
“Section 2.3, Programmable Baud Rate
Generator” on page 8
.
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see
Figure 4
). Alternatively, an external
clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates.
Typical oscillator connections are shown in
Figure 4
. For further reading on oscillator circuit please see
application note DAN108 on EXAR’s web site.
Crystal Oscillator or External Clock
2.3
The UART has its own Baud Rate Generator (BRG). The BRG divides the input crystal or external clock by a
programmable divisor between 1 and (2
16
-1) to obtain a 16X sampling clock of the serial data rate. The
sampling clock is used by the transmitter for data bit shifting and
receiver for data sampling. The BRG divisor
(DLL and DLM registers) defaults to a random value upon power up or a reset. Therefore, the BRG must be
programmed during initialization to the operating data rate. Programming the Baud Rate Generator Registers
DLM and DLL provides the capability of selecting the operating data rate.
Table 1
shows the standard data
rates available with a 14.7456 MHz crystal or external clock at 16X clock rate. When using a non-standard data
rate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation.
Programmable Baud Rate Generator
F
IGURE
4. T
YPICAL
OSCILLATOR
CONNECTIONS
divisor (decimal) = (XTAL1 clock frequency) / (serial data rate x 16)
C1
22-47pF
C2
22-47pF
Y1
1.8432 MHz
to
24 MHz
R1
0-120
(Optional)
R2
500K - 1M
XTAL1
XTAL2
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