
April 2000
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This is preliminary information on a new product now in development. Details are subject to change without notice.
Rev. 1.1
ST10R172L
16-BIT LOW VOLTAGE ROMLESS MCU
PRODUCT PREVIEW
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High Performance 16-bit CPU
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CPU Frequency: 0 to 50 MHz
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40ns instruction cycle time at 50-MHz CPU
clock
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4-stage pipeline
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Register-based design with multiple
variable register banks
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Enhanced boolean bit manipulation
facilities
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Additional instructions to support HLL and
operating systems
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Single-cycle context switching support
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1024 bytes on-Chip special function
register area
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Memory Organisation
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1KByte on-chip RAM
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Up to 16 MBytes linear address space for
code and data (1 MByte with SSP used)
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External Memory Interface
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Programmable external bus characteristics
for different address ranges
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8-bit or 16-bit external data bus
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Multiplexed or demultiplexed external
address/data buses
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Five programmable chip-select signals
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Hold and hold-acknowledge bus arbitration
support
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One Channel PWM Unit
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Fail Safe Protection
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Programmable watchdog timer
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Oscillator Watchdog
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Interrupt
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8-channel interrupt-driven single-cycle data
transfer facilities via peripheral event
controller (PEC)
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16-priority-level interrupt system with 17
sources, sample-rate down to 40 ns
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Timers
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Two multi-functional general purpose timer
units with 5 timers
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Clock Generation via on-chip PLL, or via
direct or prescaled clock input
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Serial Channels
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Synchronous/asynchronous
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High-speed-synchronous serial port SSP
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Up to 77 general purpose I/O lines
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No bootstrap loader
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Electrical Characteristics
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5V Tolerant I/Os
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5V Fail-Safe Inputs (Port 5)
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Power: 3.3 Volt +/-0.3V
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Idle and power down modes
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Support
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C-compilers, macro-assembler packages,
emulators, evaluation boards, HLL-
debuggers, simulators, logic analyser
disassemblers, programming boards
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Package
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100-Pin Thin Quad Flat Pack (TQFP)
ST10 CORE
DPRAM
Interrupt Controller
&PEC
P.4
P.1
P.0
Po.2
P.6
P.3
Dpins
ASC
GPT1/2
WDT
XSSP
P.5
OSC
PLL
P.7
PWM
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