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參數(shù)資料
| 型號： | SSTVF16857EV |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs |
| 中文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56 |
| 封裝： | 4.50 X 7 MM, 0.65 MM HEIGHT, PLASTIC, MO-225, SOT-702-1, VFBGA-56 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 117K |
| 代理商： | SSTVF16857EV |
Philips Semiconductors
Product data
SSTVF16857
DDR PC1600-PC3200 14-bit SSTL_2 registered
driver with differential clock inputs
2
2003 Sep 19
FEATURES
Stub-series terminated logic for 2.5 V V
DDQ
(SSTL_2)
Optimized for PC 2700 DDR (Double Data Rate) SDRAM
applications
Suitable for PC1600/PC2100 DDR SDRAM applications
Suitable for PC3200 applications when used at V
DD
= 2.6 V
Inputs compatible with JESD8-9 SSTL_2 specifications.
Flow-through architecture optimizes PCB layout
ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
Latch-up testing is done to JEDEC Standard JESD78, which
exceeds 100 mA.
Full DDR300/333/400 solution @ 2.5V when used with PCKV857
Available in TSSOP-48, TVSOP-48 and 56 ball VFBGA packages
Superior VREF noise rejection
DESCRIPTION
The SSTVF16857 is a 14-bit SSTL_2 registered driver with
differential clock inputs, designed to operate between 2.3 V and
2.7 V. V
DDQ
must not exceed V
CC
. Inputs are SSTL_2 type with
V
REF
normally at 0.5*V
DDQ
. The outputs support class I which can
be used for standard stub-series applications or capacitive loads.
Master reset (RESET) asynchronously resets all registers to zero.
The SSTVF16857 is intended to be incorporated into standard
DIMM (Dual In-Line Memory Module) designs defined by JEDEC,
such as DDR (Double Data Rate) SDRAM or SDRAM II Memory
Modules. Different from traditional SDRAM, DDR SDRAM transfers
data on both clock edges (rising and falling), thus doubling the peak
bus bandwidth. A DDR DRAM rated at 166 MHz will have a burst
rate of 333 MT/s (mega-transfers per second). The modules require
between 23 and 27 registered control and address lines, so two
14-bit wide devices will be used on each module. The SSTVF16857
is intended to be used for SSTL_2 input and output signals.
The device data inputs consist of differential receivers. One
differential input is tied to the input pin while the other is tied to a
reference input pad, which is shared by all inputs.
The clock input is fully differential to be compatible with DRAM
devices that are installed on the DIMM. However, since the control
inputs to the SDRAM change at only half the data rate, the device
must only change state on the positive transition of the CLK signal.
In order to be able to provide defined outputs from the device even
before a stable clock has been supplied, the device must support an
asynchronous input pin (reset), which when held to the LOW state
will assume that all registers are reset to the LOW state and all
outputs drive a LOW signal as well.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
V
DDQ
Q5
Q6
Q9
Q10
D12
D11
D10
D9
D8
RESET
V
REF
GND
V
CC
CLK+
CLK-
D7
D6
D5
D4
D3
V
CC
GND
D2
D1
21
22
23
24
25
26
27
28
V
DDQ
Q14
D14
D13
GND
V
CC
Q1
Q2
GND
Q3
Q4
GND
V
DDQ
Q7
V
DDQ
GND
Q8
V
DDQ
GND
Q11
Q12
GND
Q13
SW00685
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
=t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
C
I
Propagation delay; CLK to Qn
C
L
= 30 pF; V
DDQ
= 2.5 V
V
CC
= 2.5 V
1.9
ns
Input capacitance
2.9
pF
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參數(shù)描述 |
|---|---|
| SSTVF16857EV,518 | 功能描述:寄存器 DDR2700-3200 SSTL2 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTVF16857EV-T | 功能描述:寄存器 DDR2700-3200 SSTL2 REGDRV DIFF RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTVF16859 | 制造商:PHILIPS-SEMI 功能描述: |
| SSTVF16859_05 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:13-bit 1 : 2 SSTL_2 registered buffer for DDR |
| SSTVF16859BG | 功能描述:IC REGISTER BUFF 13-26B 64-TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:74SSTVF 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
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