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參數(shù)資料
| 型號： | SSTV16859MTDX |
| 元件分類： | 通用總線功能 |
| 英文描述： | 1-Mbit (64K x 16) Static RAM |
| 中文描述： | 記憶體驅動 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 76K |
| 代理商： | SSTV16859MTDX |
2001 Fairchild Semiconductor Corporation
DS500387
www.fairchildsemi.com
September 2000
Revised February 2001
S
SSTV16857
14-Bit Register with SSTL-2 Compatible I/O and Reset
General Description
The SSTV16857 is a 14-bit register designed for use with
184 and 232 pin DDR-I memory modules. The device has
a differential input clock, SSTL-2 compatible data inputs
and a LVCMOS compatible RESET input. The device has
been designed for compliance with the JEDEC DDR mod-
ule and register specifications.
The device is fabricated on an advanced submicron CMOS
process and is designed to operate at power supplies of
less than 3.6V’s.
Features
I
Compliant with DDR-I registered module specifications
I
Operates at 2.5V
±
0.2V V
DD
I
SSTL-2 compatible input and output structure
I
Differential SSTL-2 compatible clock inputs
I
Low power mode when device is reset
I
Industry standard 48 pin TSSOP package
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter
“
X
”
to the ordering code.
Connection Diagram
Pin Descriptions
Truth Table
L
=
Logic LOW
H
=
Logic HIGH
X
=
Don
’
t Care, but not floating unless noted
↑
=
LOW-to-HIGH Clock Transition
↓
=
HIGH-to-LOW Clock Transition
Order Number
SSTV16857MTD
Package Number
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Name
Q
1
-Q
14
D
1
-D
14
RESET
CK
Description
SSTL-2 Compatible Output
SSTL-2 Compatible Inputs
Asynchronous LVCMOS Reset Input
Positive Master Clock Input
CK
V
REF
V
DDQ
V
DD
Negative Master Clock Input
Voltage Reference Pin for SSTL Level Inputs
Power Supply Voltage for Output Signals
Power Supply Voltage for Inputs
RESET
L
D
n
X or
Floating
L
H
X
X
CK
X or
Floating
↑
↑
L
H
CK
X or
Floating
↓
↓
H
L
Q
n
L
H
H
H
H
L
H
Q
n
Q
n
相關PDF資料 |
PDF描述 |
|---|---|
| SSTV16859 | Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset |
| SSTV16859G | Voltage Regulator IC; Output Current:300mA; Package/Case:8-MSOP; Supply Voltage Max:6V; Current Rating:300mA; Leaded Process Compatible:No; Output Current Max:300mA; Output Voltage Max:5V; Output Voltage Min:1.215V |
| SSTV16859MTD | Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset |
| SSTVF16857 | DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs |
| SSTVF16857DGG | DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SSTVA16857AG | 功能描述:IC REGIST BUFF 14BIT DDR 48TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTVA16857AGLF | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTVA16857AGLFT | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTVA16857AGT | 功能描述:IC REGIST BUFF 14BIT DDR 48TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTVA16859AG | 功能描述:IC BUFFER DDR 13-26BIT 64-TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
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