參數(shù)資料
型號: SST89E54RD2A-40-I-NJE
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44
封裝: ROHS COMPLIANT, PLASTIC, MS-018AC, LCC-44
文件頁數(shù): 43/84頁
文件大?。?/td> 1755K
代理商: SST89E54RD2A-40-I-NJE
48
Data Sheet
FlashFlex MCU
SST89E54RD2A/RDA / SST89E58RD2A/RDA
SST89V54RD2A/RDA / SST89V58RD2A/RDA
2007 Silicon Storage Technology, Inc.
S71339-01-000
1/07
7.0 WATCHDOG TIMER
The device offers a programmable Watchdog Timer (WDT)
for fail safe protection against software deadlock and auto-
matic recovery.
To protect the system against software deadlock, the user
software must refresh the WDT within a user-defined time
period. If the software fails to do this periodical refresh, an
internal hardware reset will be initiated if enabled (WDRE=
1). The software can be designed such that the WDT times
out if the program does not work properly.
The WDT in the device uses the system clock (XTAL1) as
its time base. So strictly speaking, it is a watchdog counter
rather than a watchdog timer. The WDT register will incre-
ment every 344,064 crystal clocks. The upper 8-bits of the
time base register (WDTD) are used as the reload register
of the WDT.
The WDTS flag bit is set by WDT overflow and is not
changed by WDT reset. User software can clear WDTS by
writing “1” to it.
Figure 7-1 provides a block diagram of the WDT. Two SFRs
(WDTC and WDTD) control watchdog timer operation.
During idle mode, WDT operation is temporarily sus-
pended, and resumes upon an interrupt exit from idle.
The time-out period of the WDT is calculated as follows:
Period = (255 - WDTD) * 344064 * 1/fCLK (XTAL1)
where WDTD is the value loaded into the WDTD register
and fOSC is the oscillator frequency.
FIGURE
7-1: Block Diagram of Programmable Watchdog Timer
1339 F22.0
WDT Upper Byte
WDT Reset
Internal Reset
344064
clks
Counter
CLK (XTAL1)
Ext. RST
WDTC
WDTD
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