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參數(shù)資料
| 型號： | SST85LD1008M-60-PC-LBTE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91 |
| 封裝： | 12 X 24 MM, ROHS COMPLIANT, MO-210, LBGA-91 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大小： | 211K |
| 代理商： | SST85LD1008M-60-PC-LBTE |
Fact Sheet
1 GByte / 2 GByte / 4 GByte / 8 GByte NANDrive
SST85LD1001K / SST85LD1002L / SST85LD1004M /SST85LD1008M
2008 Silicon Storage Technology, Inc.
S71319(01)-04-000
11/08
8
5.0 CONFIGURABLE WRITE PROTECT/
POWER-DOWN MODES
The WP#/PD# pin can be used for either Write Protect
mode or Power-down mode, but only one mode is active at
any time. Either mode can be selected through the host
command, Set-WP#/PD#-Mode.
Once the mode is set with this command, the device will
stay in the configured mode until the next time this
command is issued. Power-off or reset will not change the
configured mode.
5.1 Write Protect Mode
When the device is configured in the Write Protect mode,
the WP#/PD# pin offers extended data protection. This
feature can be either selected through a jumper or host
logic to protect the stored data from inadvertent system
writes or erases, and viruses. The Write Protect feature
protects the full address space of the data stored on the
flash media.
In the Write Protect mode, the WP#/PD# pin should be
asserted prior to issuing the destructive commands: Erase-
Sector, Format-Track, Write-DMA, Write-Multiple, Write-
Multiple-without-Erase,
Write-Sector(s),
Write-Sector-
without-Erase, or Write-Verify. This will force the NANDrive
to reject any destructive commands from the ATA interface.
All destructive commands will return 51H in the Status
register and 04H in the Error register signifying an invalid
command. All non-destructive commands will be executed
normally.
5.2 Power-down Mode
When the device is configured in the Power-down mode, if
the WP#/PD# pin is asserted during a command, the
NANDrive completes the current command and returns to
the standby mode immediately to save power. Afterwards,
the device will not accept any other commands. Only a
Power-on Reset (POR) or hardware reset will bring the
device to normal operation with the WP#/PD# pin de-
asserted.
6.0 POWER-ON INITIALIZATION
NANDrive is self-initialized during the first power-up. As
soon as the power is applied to the NANDrive it reports
busy for typically up to five seconds while performing bad
blocks search and low level format. This initialization is a
one time event.
During the first self-initialization, the NANDrive firmware
scans all connected flash media devices and reads their
device ID. If the device ID matches the listed flash media
devices, the NANDrive performs drive recognition based
on the algorithm provided by the flash media suppliers,
including setting up the bad block table, executing all the
necessary handshaking routines for flash media support,
and, finally, performing the low-level format.
If the drive initialization fails, and a visual inspection is
unable to determine the problem, SST provides a
comprehensive interface for manufacturing flow debug.
This interface not only allows debug of the failure and
manual reset of the initialization process, but also allows
customization of user definable options.
6.1 ATA/IDE Interface
The
ATA
interface
can
be
used
for
NANDrive
manufacturing support. SST provides an example of a
DOS-based
solution
(an
executable
routine)
for
manufacturing debug and rework.
6.2 Serial Communication Interface (SCI)
For additional manufacturing flexibility, the SCI bus can be
used for manufacturing error reporting and for accessing
the status of the controller’s internal activities. The SCI
consists of 3 active signals: SCIDOUT, SCIDIN, and
SCICLK. Always provide access to the SCI interface in the
PCB design to aid in design validation.
7.0 LIFETIME EXPECTANCY
NANDrive with advanced NAND management technology
significantly extends the life of a product with its extensive
ECC, advanced wear-leveling, and data scan and Refresh
(DSR) algorithms. Each NANDrive device is partitioned
into four wear-leveling groups. See Table 4-4 for the group
size of each product.
Each NANDrive wear-leveling group can receive at least 10
million write cycles from the host. With four wear-leveling
groups in each product, 40 million write cycles per product
is possible when host writes are evenly distributed across
groups.
For applications where data security is essential, NANDrive
with advanced NAND management technology offers two
additional protection features—protection zones and
password protections.
Protection zones - Up to four independent protection zones
can be enabled as either Read-only or Hidden (Read/Write
protected). If the zones are not enabled, the data is
unprotected (default configuration).
Password Protection - Requires a customer-unique
password to access information within the protected zones.
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| SST85LD1008M-60-PC-LCTE | 功能描述:閃存 8G NAND 60ns 3.3V Industrial RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST85LP1004A-M-C-LBTE | 功能描述:閃存 4GB NANDrive 3.3V RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST85LP1016B-M-C-FTE | 功能描述:閃存 16G NAND 3.3V Commercial RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST88VP1107 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:All-in-OneMemory |
| SST88VP1107-80-5C-LBSE | 功能描述:組合存儲器 NOR/NAND/PSRAM 80MHz 2.7V Commercial RoHS:否 制造商:Microchip Technology 組織:512 K x 16 電源電壓-最大: 電源電壓-最小: 最大工作溫度:+ 85 C 最小工作溫度:- 20 C 封裝 / 箱體:LFBGA-48 封裝:Tray |
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