參數(shù)資料
型號： SST55VD020-60-C-MVWE
廠商： SILICON STORAGE TECHNOLOGY INC
元件分類： 存儲控制器/管理單元
英文描述： IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA85
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-225, VFBGA-85
文件頁數(shù)： 43/45頁
文件大?。?/td> 666K
代理商： SST55VD020-60-C-MVWE
Data Sheet
NAND Controller
SST55VD020
2009 Silicon Storage Technology, Inc.
S71355-03-000
07/09
7
TABLE
1: Pin Assignments (1 of 4)
Symbol
Pin No.
Pin
Type
I/O
Type1
Name and Functions
100-
TQFP
85-
VFBGA
Host Side Interface
A2
53
B2
I
I1Z
A[2:0] are used to select one of eight registers in the Task File.
A1
22
D9
A0
23
D8
D15
65
D3
I/O
I1Z/O2
D[15:0] Data bus
D14
66
E2
D13
67
E3
D12
68
F2
D11
70
F3
D10
71
G1
D9
72
G2
D8
73
G3
D7
3
J9
D6
4
H10
D5
5
H9
D4
6
H8
D3
8
G9
D2
9
G8
D1
10
F10
D0
11
F9
DMACK
20
E8
I
I2U
DMA Acknowledge - input from host
DMARQ
14
F8
O
O1
DMA Request to host
IORDY
62
D2
O
O1
IORDY: When Ultra DMA mode DMA Write is not active and the
device is not ready to respond to a data transfer request, this sig-
nal is negated to extend the Host transfer cycle. However, it is
never negated by this controller.
DDMARDY#
DDMARDY#: When Ultra DMA mode DMA Write is active, this sig-
nal is asserted by the host to indicate that the device is read to
receive Ultra DMA data-in bursts. The device may negate
DDMARDY# to pause an Ultra DMA transfer.
DSTROBE
DSTROBE: When Ultra DMA mode DMA Write is active, this sig-
nal is the data-out strobe generated by the device. Both the rising
and falling edges of DSTROBE cause data to be latched by the
host. The device may stop generating DSTROBE edges to pause
an Ultra DMA data-out burst.
CS1FX#
24
C10
II2Z
CS1FX# is the chip select for the task file registers
CS3FX#
52
B1
CS3FX# is used to select the Alternate Status register and the
Device Control register.
CSEL
56
C3
I
I1U
This internally pulled-up signal is used to configure this device as a
Master or a Slave. When this pin is grounded, this device is config-
ured as a Master. When the pin is open, or tied to VDDQ, this
device is configured as a Slave. The pin setting should remain the
same from Power-on to Power-down.
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