參數(shù)資料
型號: SST55VD020-60-C-MVWE
元件分類: 存儲控制器/管理單元
英文描述: IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA85
封裝: 6 X 6 MM, ROHS COMPLIANT, MO-225, VFBGA-85
文件頁數(shù): 23/45頁
文件大小: 666K
代理商: SST55VD020-60-C-MVWE
Data Sheet
NAND Controller
SST55VD020
2009 Silicon Storage Technology, Inc.
S71355-03-000
07/09
3
GENERAL DESCRIPTION
The NAND Controller contains a microcontroller and
embedded flash file system integrated in TQFP and
VFBGA packages. Refer to Figure 1 for the NAND Control-
ler block diagram. The controller interfaces with the host
system allowing data to be written to and read from the
flash media.
Performance-optimized NAND Controller
The NAND Controller translates standard ATA signals into
flash media data and control signals. The following compo-
nents contribute to the NAND Controller’s operation.
Microcontroller Unit (MCU)
The MCU coordinates all related components to complete
requested operations.
Internal Direct Memory Access (DMA)
The NAND Controller uses internal DMA which allows
instant data transfer from buffer to flash media. This
increases the data transfer rate by eliminating the micro-
controller overhead associated with the traditional, firm-
ware-based approach.
Power Management Unit (PMU)
The power management unit controls the power consump-
tion of the NAND Controller. It reduces the power con-
sumption of the NAND Controller by putting circuitry not in
operation into sleep mode. The PMU has zero wake-up
latency.
SRAM Buffer
The NAND Controller performs as an SRAM buffer to opti-
mize the host’s data transfer to and from the flash media.
Embedded Flash File System
The embedded flash file system is an integral part of the
NAND Controller. It contains MCU firmware that performs
the following tasks:
1. Translates host side signals into flash media
Writes and Reads.
2. Provides dynamic flash media wear-leveling to
spread the flash writes across all unused memory
address space to increase the longevity of flash
media.
3. Keeps track of data file structures.
Error Correction Code (ECC)
The NAND Controller uses BCH Error Detection Code
(EDC) and Error Correction Code (ECC) algorithms
which correct up to eight random single-bit errors for
each 512-byte block of data.
High performance is achieved through hardware-based
error detection and correction.
Serial Communication Interface (SCI)
The Serial Communication Interface (SCI) is designed to
provide trace information during debugging process. To aid
in validation, always provide the SCI access to PCB
design.
Programmable, Multi-tasking NAND Interface
The multi-tasking interface enables fast, sustained write
and read performance by allowing multiple Read, Program,
and Erase operations to multiple flash media devices. The
programmable NAND interface enables timely support of
fast changing NAND technology.
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