參數(shù)資料
型號(hào): SST55LD019C-45-I-BWE
廠商: SILICON STORAGE TECHNOLOGY INC
元件分類: 存儲(chǔ)控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PBGA84
封裝: LEAD FREE, MO-210, TFBGA-84
文件頁數(shù): 62/76頁
文件大?。?/td> 711K
代理商: SST55LD019C-45-I-BWE
Advance Information
ATA Flash Disk Controller
SST55LD019A / SST55LD019B / SST55LD019C
2004 Silicon Storage Technology, Inc.
S71241-02-000
4/04
65
12.2 AC Characteristics
FIGURE
12-1: AC INPUT/OUTPUT REFERENCE WAVEFORMS
12.2.1 Host Side Interface I/O Input (Read) Timing Specification
Note: The maximum load on IOCS16# is 1 LSTTL with 50pF total load.
All AC specifications are guaranteed by design.
FIGURE
12-2: HOST SIDE INTERFACE I/O READ TIMING DIAGRAM
TABLE
12-7: HOST SIDE INTERFACE I/O READ TIMING
Symbol
Parameter
Min
Max
Units
TSU (IORD#)
Data Setup before IORD#
20
-
ns
TH (IORD#)
Data Hold following IORD#
5
-
ns
TW (IORD#)
IORD# Width Time
70
-
ns
TSUA (IORD#)
Address Setup before IORD#
25
-
ns
THA (IORD#)
Address Hold following IORD#
10
-
ns
TDF IOCS16#(ADR) IOCS16# Delay Falling from Address
-
20
ns
TDR IOCS16#(ADR) IOCS16# Delay Rising from Address
-
20
ns
T12-7.0 1241
1241 F02.0
REFERENCE POINTS
OUTPUT
INPUT
VIT
VIHT
VILT
VOT
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference
points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10%
90%) are <10 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
1241 F03.0
TDR IOCS16#(ADR)
TDF IOCS16#(ADR)
THA (IORD#)
TH (IORD#)
TSUA (IORD#)
T
SU (IORD#)
TW (IORD#)
Valid Address1
IORD#
IOCS16#
D15-D0
DOUT
1. Valid Address consists of signals CS1FX#, CS3FX# and A2-A0.
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