參數(shù)資料
型號(hào): SST55LD019A-45-C-TQPE
廠商: SILICON STORAGE TECHNOLOGY INC
元件分類: 存儲(chǔ)控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PQFP64
封裝: LEAD FREE, MS-026ADC, TQFP-64
文件頁數(shù): 66/76頁
文件大小: 711K
代理商: SST55LD019A-45-C-TQPE
Advance Information
ATA Flash Disk Controller
SST55LD019A / SST55LD019B / SST55LD019C
2004 Silicon Storage Technology, Inc.
S71241-02-000
4/04
69
FIGURE
12-7: HOST TERMINATES A MULTI-WORD DMA DATA TRANSFER
12.2.4 Media Side Interface I/O Timing Specifications
Note: All AC specifications are guaranteed by design.
TABLE 12-10: SST55LD019A/B/C TIMING PARAMETERS
Symbol
Parameter
Min
Max
Units
TCLS
FCLE Setup Time
30
-
ns
TCLH
FCLE Hold Time
30
-
ns
TCS
FCE# Setup Time
30
-
ns
TCH
FCE# Hold Time for Command/Data Write Cycle
30
-
ns
TCHR
FCE# Hold Time for Sequential Read Last Cycle
-
30
ns
TWP
FWE# Pulse Width
30
-
ns
TWH
FWE# High Hold Time
30
-
ns
TWC
Write Cycle Time
60
-
ns
TALS
FALE Setup Time
30
-
ns
TALH
FALE Hold Time
30
-
ns
TDS
FAD[15:0] Setup Time
25
-
ns
TDH
FAD[15:0] Hold Time
25
-
ns
TRP
FRE# Pulse Width
30
-
ns
TRR
Ready to FRE# Low
30
-
ns
TREA
FRE# Data Setup Access Time
20
-
ns
TRC
Read Cycle Time
60
-
ns
TREH
FRE# High Hold Time
30
-
ns
TRHZ
FRE# High to Data Hi-Z
5
-
ns
T12-10.0 1241
Write DQ15-0
Read DQ15-0
IORD#/IOWR
DMACK#
DMARQ
CS1FX#/CS3FX#
1241 F08.0
T0
TD
TK
TE
TN
TZ
TJ
TF
TH
TG
Note: 1. To terminate the transmission of a data burst, the host should negate DMACK# within the
specified time after a IORD# or IOWR# pulse. No further IORD# or IOWR# pulses shall be
asserted for this burst.
2. If the device is able to continue the transfer of data, the device may leave DMARQ asserted
and wait for the host to reassert DMACK# or may negate DMARQ at any time after detecting
that DMACK# has been negated.
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