參數(shù)資料
型號： SST26WF032-80-4I-QAE
廠商： SILICON STORAGE TECHNOLOGY INC
元件分類： PROM
英文描述： 32M X 1 SPI BUS SERIAL EEPROM, PDSO8
封裝： 6 X 5 MM, ROHS COMPLIANT, WSON-8
文件頁數(shù)： 8/36頁
文件大?。?/td> 1339K
代理商： SST26WF032-80-4I-QAE
2010 Silicon Storage Technology, Inc.
S71409-01-000
01/10
16
1.8V Serial Quad I/O (SQI) Flash Memory
SST26WF032
Advance Information
Set Burst
The Set Burst command specifies the number of bytes to be output during a Read Burst command
before the device wraps around. To set the burst length the host drives CE# low, sends the Set Burst
command cycle (C0H) and one data cycle, then drives CE# high. A cycle is two nibbles, or two clocks,
long, most significant nibble first. After power-up or reset, the burst length is set to eight Bytes (00H).
See Table 4 for burst length data and Figure 12 for the sequence.
Figure 12:Set Burst Length Sequence
Read Burst
To execute a Read Burst operation the host drives CE# low, then sends the Read Burst command
cycle (0CH), followed by three address cycles, and then one dummy cycle. Each cycle is two nibbles
(clocks) long, most significant nibble first.
After the dummy cycle, the device outputs data on the falling edge of the SCK signal starting from the
specified address location. The data output stream is continuous through all addresses until termi-
nated by a low-to-high transition on CE#.
During Read Burst, the internal address pointer automatically increments until the last byte of the burst
is reached, then jumps to first byte of the burst. All bursts are aligned to addresses within the burst
length, see Table 5. For example, if the burst length is eight Bytes, and the start address is 06h, the
burst sequence would be: 06h, 07h, 00h, 01h, 02h, 03h, 04h, 05h, 06h, etc. The pattern would repeat
until the command was terminated by a low-to-high transition on CE#.
During this operation, blocks that are Read-locked will output data 00H.
Table 4: Burst Length Data
Burst Length
High Nibble (H0)
Low Nibble (L0)
8 Bytes
0h
16 Bytes
0h
1h
32 Bytes
0h
2h
64 Bytes
0h
3h
T4.0 1409
Table 5: Burst Address Ranges
Burst Length
Burst Address Ranges
8 Bytes
00-07H, 08-0FH, 10-17H, 18-1FH...
16 Bytes
00-0FH, 10-1FH, 20-2FH, 30-3FH...
32 Bytes
00-1FH, 20-3FH, 40-5FH, 60-7FH...
64 Bytes
00-3FH, 40-7FH, 80-BFH, C0-FFH
T5.0 1409
1409 F32.0
MODE 3
0
1
SCK
SIO(3:0)
CE#
C1 C0
MODE 0
23
H0 L0
MSN LSN
Note: MSN = Most Significant Nibble,
LSN = Least Significant Nibble
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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SST270-E3 功能描述:JFET 45V 2mA RoHS:否 制造商:ON Semiconductor 晶體管極性:N-Channel 漏極電流（Vgs=0 時的 Idss）:50 mA 漏源電壓 VDS:15 V 閘/源擊穿電壓: 漏極連續(xù)電流:50 mA 配置: 安裝風(fēng)格: 封裝 / 箱體:SC-59 封裝:Reel
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