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參數(shù)資料
| 型號： | SSM2517CBZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 0K |
| 描述： | IC AMP AUDIO 2.4W MONO D 9WLCSP |
| 產(chǎn)品變化通告： | 8mm Carrier Tape Changes 28/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | D 類 |
| 輸出類型： | 1-通道（單聲道） |
| 在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： | 2.4W x 1 @ 4 歐姆 |
| 電源電壓： | 2.5 V ~ 5.5 V |
| 特點(diǎn)： | 消除爆音，數(shù)字輸入，短路和熱保護(hù)，關(guān)機(jī) |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 9-WLCSP（1.46x1.46） |
| 封裝/外殼： | 9-WFBGA，CSPBGA |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | SSM2517CBZ-R7DKR |
Data Sheet
SSM2517
Rev. B | Page 13 of 16
THEORY OF OPERATION
MASTER CLOCK
The SSM2517 requires a clock present at the PCLK input pin.
This clock must be fully synchronous with the incoming digital
audio on the serial interface. The clock frequencies must fall
into one of these ranges: 1.84 MHz to 3.23 MHz or 3.68 MHz
to 6.46 MHz.
POWER SUPPLIES
The SSM2517 requires two power supplies: PVDD and VDD.
PVDD
The PVDD pin supplies power to the full-bridge power stage
of a MOSFET and its associated drive, control, and protection
circuitry. It also supplies power to the digital-to-analog converter
(DAC) and to the Class-D PDM modulator. PVDD can operate
from 2.5 V to 5.5 V and must be present to obtain audio output.
Lowering the supply voltage of PVDD results in lower maximum
output power and, therefore, lower power consumption.
VDD
The VDD pin provides power to the digital logic circuitry.
VDD can operate from 1.62 V to 3.6 V and must be present
to obtain audio output. Lowering the supply voltage of VDD
results in lower power consumption but does not affect audio
performance.
POWER CONTROL
On device power-up, PVDD must first be applied to the device,
which latches in the designated GAIN_FS pin functionality.
The SSM2517 contains a smart power-down feature. When
enabled, the smart power-down feature looks at the incoming
digital audio and, if it receives the PDM stop condition of at
least 128 repeated 0xAC bytes (1024 clock cycles), it places the
SSM2517 in the standby state. In the standby state, the PCLK can
be removed, resulting in a full power-down state. This state is
the lowest power condition possible. When the PCLK is turned
on again and a single non-stop condition input is received, the
SSM2517 leaves the full power-down state and resumes normal
operation.
POWER-ON RESET/VOLTAGE SUPERVISOR
The SSM2517 includes an internal power-on reset and voltage
supervisor circuit. This circuit provides an internal reset to all
circuitry whenever PVDD or VDD is substantially below the
nominal operating threshold. This circuit simplifies supply
sequencing during initial power-on.
The circuit also monitors the power supplies to the SSM2517. If
the supply voltages fall below the nominal operating threshold,
this circuit stops the output and issues a reset. This ensures that
no damage occurs due to low voltage operation and that no
pops can occur under nearly any power removal condition.
SYSTEM GAIN/INPUT FREQUENCY
The GAIN_FS pin is used to set the internal gain and filtering
configuration for different sample rates of the SSM2517. This pin
can be set to one of four states by connecting the pin to PVDD or
PGND (see Table 7). The internal gain and filtering can also be
set via PDM pattern control, allowing these settings to be modi-
fied during operation (see the PDM Pattern Control section).
Table 7. GAIN_FS Function Descriptions
Device Setting
GAIN Pin Configuration
fS = 64 × PCLK, Gain = 5 V
Pull up to PVDD with a 47 kΩ
resistor
fS = 128 × PCLK, Gain = 5 V
Pull down to PGND with a 47 kΩ
resistor
fS = 64 × PCLK, Gain = 3.6 V
Pull up to PVDD
fS = 128 × PCLK, Gain = 3.6 V
Pull down to PGND
The SSM2517 has an internal analog gain control such that
when GAIN_FS is tied to PGND or PVDD via a 47 kΩ resistor
(5 V gain setting), a 6.02 dBFS PDM input signal results in
an amplifier output voltage of 5 V peak. This setting should
produce optimal noise performance when PVDD = 5 V.
When the GAIN_FS pin is tied directly to PGND or PVDD, the
gain is adjusted so that a 6.02 dBFS PDM input signal results
in an amplifier output voltage of 3.6 V peak. This setting should
produce optimal noise performance when PVDD = 3.6 V.
The SSM2517 can handle input sample rates of 64 × fS (~3 MHz)
and 128 × fS (~6 MHz). Different internal digital filtering is used
in each of these cases. Selection of the sample rate is also set via
the GAIN_FS pin (see Table 7).
Because the 64 × fS mode provides better performance with lower
power consumption, its use is recommended. The 128 × fS mode
should be used only when overall system noise performance is
limited by the source modulator.
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