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參數(shù)資料
| 型號： | SPT8000SIT |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | PLASTIC, TQFP-44 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大小： | 130K |
| 代理商： | SPT8000SIT |
11
10/12/01
SPT8000
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE
SPT8000SIT
–40 to +85 °C
44L TQFP
remains High until it completes the calibration. The
internal calibration routine takes approximately
74.5 ms for 20 MHz clock input. The SPT8000
ignores the Analog Input when BUSY is High.
When BUSY is Low, it is ready to convert the
Analog Input.
CAL
Calibration Start Input. Holding CAL High for more
than two falling edges of CLK, while RESETB is
High, initiates the SPT8000’s internal calibration
routine.
RESETB
Reset Input (active Low). Logic 0 on this
asynchronous reset pin will set the internal digital
state machine to its initial state and clear all
internal calibration coefficients.
VBS
Noise Reduction Pin. Connect a noise reduction
capacitor of 4.7 F or larger from this pin to
AGND.
CM
Common Mode Level Output. +2.25 V nominal.
Connect a noise reduction capacitor of 4.7 F or
larger from this pin to AGND.
VRC
Lower Reference. +1.25 V nominal. This voltage
sets the lower bound of analog input span.
Connect a noise reduction capacitor of 4.7 F or
larger from this pin to AGND.
VRT
Upper Reference. +3.25 V nominal. This voltage
sets the upper bound of analog input span.
Connect a noise reduction capacitor of 4.7 F or
larger from this pin to AGND.
VIN+
Analog Input Pin (+). The nominal span at this pin
is +1.25 V to +3.25 V.
VIN–
Analog Input Pin (–). The nominal span at this pin
is +3.25 V to +1.25 V.
VREF/EXTB Voltage Reference I/O Pin. +1.00 V nominal. The
voltage at this pin sets the span above and below
CM for each analog input pin. Driving VREF/EXTB
to 0 V will disable internal buffers driving VRT and
VRC, allowing the user to drive VRT and VRC
externally. Connect a noise reduction capacitor of
4.7 F or larger from this pin to AGND.
PIN ASSIGNMENTS
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
AGND
BGND
N/C
AVDD
AGND
AVDD
CLK
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D1
1
AGND
N/C
BGND
AVDD
CAL
BUSY
OTR
D13 (MSB)
D12
V
REF
/EXTB
N/C
V
IN
V
IN
+
N/C
V
RT
V
RC
N/C
V
BS
AVDD
OGND
OVDD
RESETB
AVDD
CM
N/C
SPT8000
PIN FUNCTIONS
Name
Description
AGND
Ground
AVDD
+5 V Supply
N/C
No Connect. Leave the pin open or tie it to AGND.
BGND
Ground
CLK
Clock Input
OGND
Ground for BUSY, OTR, and Data Bit Outputs
OVDD
+3.3 V to +5 V Supply for BUSY, OTR, and Data
Bit Outputs
D0–D13
Data Bit Outputs. D0=LSB, D13=MSB
OTR
Out of Range Output. OTR goes High for the
Analog input above (overrange) or below
(underrange) the full-scale range. The
corresponding Data Bit Outputs are all 1s for
overrange, and all 0s for underrange.
BUSY
Busy Output. BUSY goes High when the SPT8000
goes into its internal calibration routine and
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR
USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR
THE RIGHTS OF OTHERS.
www.fairchildsemi.com
Copyright 2002 Fairchild Semiconductor Corporation
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