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參數(shù)資料
| 型號： | SPT7852 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | DUAL 10-BIT, 20 MSPS, 160 mW A/D CONVERTER |
| 中文描述： | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | TQFP-44 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 67K |
| 代理商： | SPT7852 |
9
1/12/00
SPT7852
CALIBRATION
The SPT7852 uses an auto-calibration scheme to ensure
10-bit accuracy over time and temperature. Gain and offset
errors are continually adjusted to 10-bit accuracy during de-
vice operation. This process is completely transparent to the
user.
Upon powerup, the SPT7852 begins its calibration algo-
rithm. In order to achieve the calibration accuracy required,
the offset and gain adjustment step size is a fraction of a 10-
bit LSB. Since the calibration algorithm is an oversampling
process, a minimum of 10k clock cycles are required. This
results in a minimum calibration time upon powerup of 250
μ
sec (for a 20 MHz sample rate). Once calibrated, the
SPT7852 remains calibrated over time and temperature.
Since the calibration cycles are initiated on the rising edge
of the clock, the clock must be continuously applied for the
SPT7852 to remain in calibration.
INPUT PROTECTION
All I/O pads are protected with an on-chip protection circuit
shown in figure 7. This circuit provides ESD robustness to
3.5 kV and prevents latch-up under severe discharge condi-
tions without degrading analog transition times.
Figure 7 – On-Chip Protection Circuit
V
DD
Analog
Pad
120
120
POWER SUPPLY SEQUENCING
CONSIDERATIONS
All logic inputs should be held low until power to the device
has settled to the specific tolerances. Avoid power decou-
pling networks with large time constants which could delay
V
DD
power to the device.
DIGITAL OUTPUTS, DATA VALID,
AND MSB INVERT
The output data for both channels can be latched using the
rising edge of Data Valid (DAV). Refer to table II for mini-
mum data setup and hold times. The format of the data is
straight binary when the MSB Invert pin (MSBINV) is held
low and Two’s Complement format when MSB Invert is
high.
OVERRANGE OUTPUT
An OVERRANGE OUTPUT from D10A or D10B is an indi-
cation that the analog input signal has exceeded the posi-
tive full-scale input voltage by 1 LSB. When this condition
occurs, D10A/B will switch to logic 1. All other data outputs
(D0A/B to D9A/B) will remain at logic 1 as long as D10A/B
remains at logic 1. This feature makes it possible to include
the SPT7852 in higher resolution systems.
Table III – Output Data Information (Binary Code)
Output Code
(MSBINV=0)
D9A/B–D0A/B
11 1 1 1 1 1111
11 1 1 1 1 111
00 0000 000
00 0000 0000
Output Code
(MSBINV=1)
D9A/B–D0A/B
01 1 1 1 1 1111
01 1 1 1 1 111
10 0000 000
10 0000 0000
Overrange
D10A/B
1
0
0
0
0
Analog Input
+FS + 1/2 LSB
+FS – 1/2 LSB
[+FS –(–FS)]/2
–FS + 1/2 LSB
–FS
indicates the flickering bit between logic 0 and 1.
+FS = V
RHS
; –FS = V
RLS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SPT7852SCT | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:DUAL 10-BIT, 20 MSPS, 160 mW A/D CONVERTER |
| SPT7852SCU | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:DUAL 10-BIT, 20 MSPS, 160 mW A/D CONVERTER |
| SPT7852SIT | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:DUAL 10-BIT, 20 MSPS, 160 mW A/D CONVERTER |
| SPT7853 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:TRIPLE 10-BIT, 30 MSPS A/D CONVERTER |
| SPT7853SCT | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:TRIPLE 10-BIT, 30 MSPS A/D CONVERTER |
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