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參數(shù)資料
| 型號(hào)： | SPT7824 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | EVALUATION BOARD |
| 中文描述： | 評(píng)價(jià)委員會(huì) |
| 文件頁(yè)數(shù)： | 6/17頁(yè) |
| 文件大?。?/td> | 206K |
| 代理商： | SPT7824 |
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5/22/97
AN7820/24
Table 5: Timing Specification
Function Description
tpd1
Min
Typ
Max
Unit
SPT7820/24, CLK
to Data Valid Prop
Delay
MAX9686 Prop.
Delay
SPT7820/24, T(fall)
Prop. Delay
74F174, Prop.
Delay
74F174 Setup Time
74174, Hold Time
CLK Positive Pulse
Width (SPT7820)
CLK Negative Pulse
Width (SPT7820)
CLK Positive Pulse
width (SPT7824)
CLK Negative pulse
Width (SPT7824)
-
14
18
nsec
tdp2
-
6
9
nsec
tdp3
4.5
7
10
nsec
tdp4
4.5
4
4
7
-
-
10
-
-
nsec
nsec
nsec
ts
th
tpwH
20
-
300
nsec
tpwL
20
-
-
nsec
tpwH
10
-
300
nsec
tpwL
10
-
-
nsec
SPT7820/24 ACQUISITION TIME SPECIFICATION
Figure 8: Acquisition Time
T
acq 1
ANALOG
INPUT
CLOCK
INPUT
INTERNAL
THA OUTPUT
Settle to 1/2 LSB
Vin Hold time
(5 ns min)
INTERNAL
THA TIMING
50%
HOLD
TRACK
TpwH
T
acq 2
- 2V
+ 2V
+ FS
- FS
TRACK
The acquisition time (Tacq) is defined as the hold to track full
scale settling time for the internal track-and-hold (THA). Logic
low of the clock input corresponds to track mode and logic
high is the hold mode for the internal THA. Figure 8 shows two
types of acquisition time:
1)
Tacq 1 is the settling time of the THA when it is in track
and it is driven by the analog input switching.
2)
Tacq 2 is the amount of time it takes for the internal
THA of the ADC to reacquire the analog input when
switching from hold to track (CLK IN from high to low)
to within 1/2 LSB.
Both Tacq 1 and Tacq 2 need the same amount of time (see
the acquisition time specification in the respective data sheet).
The low-to-high clock transition should be placed after both
the analog input and internal THA are settled. The analog
input must remain for at least 5 ns (Vin hold time) after the low
to high clock transition. Keep the clock positive pulse width
(TpwH) to within the recommended limit. (Refer to the speci-
fication in the respective data sheet.)
TIMING CONSIDERATIONS WHEN USING AN
EXTERNAL TRACK-AND-HOLD
The signal-to-noise ratio (SNR) and the total harmonic distor-
tion (THD) degrade as the analog input frequency increases.
These parameters imply that the differential linearity error
(DLE) and the integral linearity error (ILE) degrades as well
at high frequency. This degradation is mainly due to aperture
jitter and/or analog input bandwidth limitation and/or slew rate
limitation of the SPT7820 and SPT7824. Below 1 MHz, the
SNR and THD of the SPT7820 and SPT7824 are generally
constant. In order to bring these accuracies up (at high
frequency), you may need to buffer the analog input using a
track-and-hold amplifier (THA). THAs can be imperfect (es-
pecially at high frequency); otherwise, the dynamic perfor-
mance of the SPT7820 or SPT7824 would be constant and
equal to its performance at 1 MHz.
Selecting an acceptable THA for a specific application is
sometimes difficult. The timing diagram shown in figure 9 and
table 6 illustrate the critical timing necessary when driving the
ADC from a THA.
Figure 9-Critical Timing Between External THA and ADC
T R A C K
H O L D
t
h1
t
acq
(ADC)
THA IN
THA OUT
THA
DIFF CLK
ADC
CLK
Droop
Pedestal
t
HTS
t
THS
t
pd1
Valid Data
Valid Data
t
HTS
ADC
OUT
Aperture delay
I
I
I
(THA
t
acq )
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