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參數(shù)資料
| 型號(hào)： | SPT7750BCU |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 8-BIT, 500 MSPS, FLASH A/D CONVERTER |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, UUC73 |
| 封裝： | DIE |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大小： | 88K |
| 代理商： | SPT7750BCU |
3
11/30/01
SPT7750
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
Unless otherwise noted, all test are pulsed
tests; therefore, T
J
= T
C
= T
A
.
LEVEL
TEST PROCEDURE
I
100% production tested at the specified temperature.
100% production tested at T
A
= +25 °C, and sample tested at the
specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteri-
zation data.
Parameter is a typical value for information purposes only.
100% production tested at T
A
= +25 °C. Parameter is guaranteed
over specified temperature range.
II
III
IV
V
VI
ELECTRICAL SPECIFICATIONS
T
J
= T
C
= T
A
= +25 °C , V
EE
=–5.2 V, V
RB
=–2.0 V, V
RM
=–1.0 V, V
RT
=0.00 V,
CLK
=500 MHz, Duty Cycle=50%, unless otherwise specified.
TEST
CONDITIONS
TEST
LEVEL
SPT7750A
TYP
SPT7750B
TYP
PARAMETERS
MIN
MAX
MIN
MAX UNITS
Dynamic Performance
Spurious Free Dynamic Range
IN
= 50 MHz
IN
= 250 MHz
I
I
49
41
44
36
dB
dB
Digital Inputs
Input High Voltage
(CLK,
CLK
)
Input Low Voltage
(CLK,
CLK
)
Clock Pulse Width High (t
PWH
)
Clock Pulse Width Low (t
PWL
)
I
–1.1
–0.7
–1.1
–0.7
V
I
I
I
–1.8
0.67
0.67
–1.5
–1.8
0.67
0.67
–1.5
V
ns
ns
1.0
1.0
1.0
1.0
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
Rise Time
Fall Time
I
I
–1.1
–0.9
–1.8
450
450
–1.1
–0.9
–1.8
450
450
V
V
ps
ps
–1.5
–1.5
20% to 80%
20% to 80%
V
V
Power Supply Requirements
Voltage V
EE
Current I
EE
Power Dissipation
IV
I
I
–4.95
–5.2
1.05
5.5
–5.45
1.2
6.25
–4.95
–5.2
1.05
5.5
–5.45 V
1.2
6.25
A
W
Typical Thermal Impedance:
θ
JC
= +4 °C/W.
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