參數(shù)資料
型號(hào): SPT7730
廠商: Fairchild Semiconductor Corporation
英文描述: 8-BIT, 3.0 MSPS, SERIAL OUTPUT A/D CONVERTER
中文描述: 8位,3.0 MSPS的,串行輸出的A / D轉(zhuǎn)換器
文件頁(yè)數(shù): 5/8頁(yè)
文件大?。?/td> 62K
代理商: SPT7730
5
12/19/97
SPT7730
Figure 1 - Analog Input Full-Scale Range
V
REF
+
6% of [(V
REF
+) - (V
REF
-)]
V
REF
-
The drive requirements for the analog input are minimal
when compared to most other converters due to the
SPT7730’s extremely low input capacitance of only 5 pF and
very high input resistance of greater than 5 M
.
+FS
-FS
F
4% of [(V
REF
+) - (V
REF
-)]
If the input buffer amplifier supply voltages are greater than
V
DD
+ 0.7 V or less than Ground - 0.7 V, the analog input
should be protected through a series resistor and a diode
clamping circuit as shown in figure 2.
Figure 2 - Recommended Input Protection Circuit
+V
47
D1
D2
ADC
Buffer
AV
DD
-V
D1 = D2 = Hewlett Packard HP5712 or equivalent
INPUT PROTECTION
All I/O pads are protected with an on-chip protection circuit
shown in figure 3. This circuit provides ESD robustness to
>3.0 kV and prevents latch-up under severe discharge
conditions without degrading analog transition times.
Figure 3 - On-Chip Protection Circuit
V
DD
Analog
Pad
120
120
MODES OF OPERATION
The SPT7730 has three modes of operation.The mode of
operation is based strictly on how the
SC
is used.
SINGLE SHOT MODE
When
SC
goes low, conversion starts on the next rising edge
of the clock (defined as the first conversion clock). The MSB
of data is valid 8 ns after the falling edge of the fourth
conversion clock. (See figure 8.)
The conversion is complete after 12 clock cycles. At the
falling edge of the twelfth clock cycle, if
SC
is high (not
selected), the data output goes to a high impedance state,
and no more conversions will take place until the next
SC
low
event. (See the single shot mode timing diagram in figure 4.)
SYNCHRONIZED MODE
When
SC
goes low, conversion will start on the next rising
edge of the clock (defined as the first conversion clock). The
MSB is valid 8 ns after the falling edge of the fourth conver-
sion clock.
The first conversion is complete after 12 clock cycles. At
any time after the falling edge of the twelfth clock cycle,
SC
may go low again to initiate the next conversion. When the
SC
goes low, the conversion starts on the rising edge of the
next clock. (See the synchronized mode timing diagram
in figure 5.)
The data output will go to a high impedance state until the
next conversion is initiated.
FREE RUN MODE
When
SC
goes low, conversion starts on the next rising edge
of the clock (defined as the first conversion clock). The MSB
data is valid 8 ns after the falling edge of the fourth conver-
sion clock.
As long as
SC
is held low, the device operates in the free run
mode. New conversions start after every twelfth cycle with
valid data available 8 ns after the falling edge of the fourth
clock within each new conversion cycle.
The data output remains low between conversion cycles.
(See the free run mode timing diagram in figure 6.)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SPT7730SCS 制造商:FAIRCHILD 制造商全稱(chēng):Fairchild Semiconductor 功能描述:8-BIT, 3.0 MSPS, SERIAL OUTPUT A/D CONVERTER
SPT7730SCU 制造商:CADEKA 制造商全稱(chēng):CADEKA 功能描述:8-BIT, 3.0 MSPS, SERIAL OUTPUT A/D CONVERTER
SPT7734 制造商:FAIRCHILD 制造商全稱(chēng):Fairchild Semiconductor 功能描述:8-BIT, 40 MSPS,175 mW A/D CONVERTER
SPT7734SCS 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 8BIT 40 MSPS SaR aDC RoHS:否 制造商:Texas Instruments 輸入信號(hào)類(lèi)型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類(lèi)型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel
SPT7734SCS_Q 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8BIT 40 MSPS SaR aDC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32