參數(shù)資料
型號: SPC560B50L5C5E0R
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-144
文件頁數(shù): 43/74頁
文件大?。?/td> 971K
代理商: SPC560B50L5C5E0R
SPC560Bx, SPC560Cx
Electrical characteristics
Doc ID 14619 Rev 4
4.18.2
DSPI characteristics
IDD_BV(ADC)
CC T
ADC supply
current on
VDD_BV
VDD = 5.5 V
Ballast static
consumption (no
conversion)
0.0409 * fperiph
mA
VDD = 5.5 V
Ballast dynamic
consumption
(continuus conversion)
0.0049 * fperiph
IDD_HV_ADC(ADC) CC T
ADC supply
current on
VDD_HV_ADC
VDD = 5.5 V
Analog static
consumption (no
conversion)
0.0017 * fperiph
VDD = 5.5 V
Analog dynamic
consumption
(continuus conversion)
0.075 * fperiph + 0.032
IDD_HV(FLASH)
CC T
CFlash +
DFlash supply
current on
VDD_HV_ADC
VDD = 5.5 V
-
8.21 (4.14 + 4.07)
IDD_HV(PLL)
CC T
PLL supply
current on
VDD_HV
VDD = 5.5 V
-
0.0031 * fperiph
1.
Operating conditions: TA = 25 °C, fperiph = 8 MHz to 64 MHz
Table 39.
On-chip peripherals current consumption(1) (continued)
Symbol
C
Parameter
Conditions
Value
Unit
Min
Typ
Max
Table 40.
DSPI characteristics
No.
Symbol
C
Parameter
Value
Unit
Min
Typ
Max
1tSCK
SR D SCK cycle time
64
ns
—fDSPI
SR D DSPI digital controller frequency
fCPU MHz
Δt
CSC
CC D
Internal delay between pad associated to SCK and
pad associated to CSn in master mode
——
120(1)
ns
2tCSCext
(2)
CC D
CS to SCK delay
Master mode
tCSCext = tCSC + ΔtCSC
ns
SR D
Slave mode
32
3tASCext
(3)
CC D
After SCK delay
Master mode
tASCext = tASC + ΔtCSC
ns
SR D
Slave mode
1/fDSPI + 5 ns
ns
4tSDC
CC D
SCK duty cycle
Master mode
tSCK/2
ns
SR D
Slave mode
tSCK/2
5tA
SR D Slave access time
27
ns
6tDI
SR D Slave SOUT disable time
0
ns
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