參數(shù)資料
型號： SPC5200CVR400R2
廠商： Freescale Semiconductor
文件頁數(shù)： 20/72頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 400MHZ 272-PBGA
標(biāo)準(zhǔn)包裝： 500
系列： MPC52xx
處理器類型： 32-位 MPC52xx PowerPC
速度： 400MHz
電壓： 1.5V
安裝類型： 表面貼裝
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 帶卷 (TR)
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
27
1.3.8.3
MUXed Mode
NOTES:
1. ACK can shorten the CS pulse width.
Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from
0–65535.
2. ACK is input and can be used to shorten the CS pulse width.
3. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration
happens the bus can be driven within 4 IPB clocks by an other modules.
Table 26. MUXed Mode Timing
Sym
Description
Min
Max
Units
Notes
SpecID
tCSA
PCI CLK to CS assertion
4.6
10.6
ns
—
A7.39
tCSN
PCI CLK to CS negation
2.9
7.0
ns
—
A7.40
tALEA
PCI CLK to ALE assertion
—3.6
ns
—
A7.41
t1
ALE assertion before Address, Bank,
TSIZ assertion
—5.7
ns
—
A7.42
t2
CS assertion before Address, Bank,
TSIZ negation
—–1.2
ns
—
A7.43
t3
CS assertion before Data wr valid
—–1.2
ns
—
A7.44
t4
Data wr hold after CS negation
tIPBIck
—ns
—
A7.45
t5
Data rd setup before CS negation
8.5
—ns
—
A7.46
t6
Data rd hold after CS negation
0
(DC + 1) × tPCIck
ns
(1),(3)
A7.47
t7
ALE pulse width
—tPCIck
ns
—
A7.48
tTSA
CS assertion after TS assertion
—6.9
ns
—
A7.49
t8
TS pulse width
—tPCIck
ns
—
A7.50
t9
CS pulse width
(2 + WS) × tPCIck (2 + WS) × tPCIck
ns
—
A7.51
tOEA
OE assertion before CS assertion
—4.7
ns
—
A7.52
tOEN
OE negation before CS negation
—5.9
ns
—
A7.53
t10
RW assertion before ALE assertion
tIPBIck
—ns
—
A7.54
t11
RW negation after CS negation
—tPCIck
ns
—
A7.55
t12
ACK assertion after CS assertion
tIPBIck
—ns
(2)
A7.56
t13
ACK negation after CS negation
—tPCIck
ns
(2)
A7.57
t14
ALE negation to CS assertion
—tPCIck
ns
A7.58
t15
ACK change before PCI clock
—2.0
ns
(2)
A7.59
t16
ACK change after PCI clock
—4.4
ns
(2)
A7.60
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