
Motorola and the stylized M Logo are registered in the U.S. Patent and Trademark Office. This
product incorporates SuperFlash
technology licensed from SST. All other product or service
names are the property of their respective owners. Motorola, Inc. 2003
DSP56857PB/D
REV 3
ORDERING INFORMATION
PACKAGE TYPE
AWARD-WINNING
DEVELOPMENT ENVIRONMENT
Processor Expert (PE) technology provides a rapid
application design (RAD) tool that combines easy-to-use
component-based software application creation with an
expert knowledge system.
The CodeWarrior Integrated Development Environment
(IDE) is a sophisticated tool for code navigation, compiling
and debugging. A comprehensive set of evaluation modules
(EVMs) and development system cards will support
concurrent engineering. Together, PE, the CodeWarrior tool
suite and EVMs create a comprehensive, scalable tools
solution for easy, fast and efficient development.
HYBRID MCU/DSP
56857
PRODUCT DOCUMENTATION
56857 PERIPHERAL CIRCUIT FEATURES
General Purpose 16-bit Quad Timer*
Two Serial Communication Interfaces
(SCI)*
Serial Peripheral Interface (SPI) Port*
Two Enhanced Synchronous Serial
Interface (ESSI) modules*
Computer Operating Properly
(COP)/Watchdog Timer
JTAG/Enhanced On-Chip Emulation
(OnCE) for unobtrusive, real-time
debugging
Six independent channels of DMA
8-bit parallel Host Interface*
Time of Day (TOD)
Four dedicated GPIO
Up to 47 GPIO
* Each peripheral I/O can be used
alternately as a General Purpose I/O
56857 MEMORY FEATURES
On-chip Memory
– 80 KB Program RAM
– 48 KB Data RAM
– 2 KB Boot ROM
– Chip Select Logic used as GPIO
Harvard architecture permits up to three
simultaneous accesses to program and
data memory
56800E CORE FEATURES
Efficient 16-bit hybrid controller engine
with dual Harvard architecture
120 Million Instructions Per Second
(MIPS) at 120MHz core frequency
Single-cycle 16
x
16-bit parallel
Multiplier-Accumulator (MAC)
Four (4) 36-bit accumulators, including
extension bits
16-bit bidirectional shifter
Parallel instruction set with unique
addressing modes
Hardware DO and REP loops
Three internal address buses and one
external address bus
Four internal data buses and one
external data bus
Instruction set supports both DSP and
controller functions
Four hardware interrupt levels
Five software interrupt levels
Controller-style addressing modes and
instructions for compact code
Efficient C compiler and local variable
support
Software subroutine and interrupt stack
with depth limited only by memory
JTAG/Enhanced OnCE debug
programming interface
The 56800E core is based on a Harvard-style architecture consisting of three execution
units operating in parallel, allowing as many as six operations per instruction cycle. The
microprocessor-style programming model and optimized instruction set allow
straightforward generation of efficient, compact code for both DSP and MCU applications.
The instruction set is also highly efficient for C compilers, enabling rapid development of
optimized control applications. Features of the 56800E core include:
DSP56800E
Reference Manual
Detailed description of the 56800E
architecture, 16-bit DSP core processor
and the instruction set
Order Number: DSP56800ERM/D
DSP5685x
User’s Manual
Detailed description of memory,
peripherals, and interfaces of the
56853, 56854, 56855, 56857, and 56858
Order Number: DSP5685xUM/D
DSP56857
Technical Data
Sheet
Electrical and timing specifications,
pin descriptions, and package
descriptions
Order Number: DSP56857/D
DSP56857
Product Brief
Summary description and block diagram
of the core, memory, peripherals
and interfaces
Order Number: DSP56857PB/D
PART
SUPPLY
VOLTAGE
PIN COUNT
FREQUENCY
(MHz)
ORDER NUMBER
DSP56857
DSP56857
1.8V, 3.3V
1.8V, 3.3V
Low-Profile Quad Flat Pack (LQFP)
Low-Profile Quad Flat Pack (LQFP)
100
100
120
120
DSP56857BU120
SPAK56857BU120
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.