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參數資料
| 型號： | SP9843BS |
| 英文描述： | 8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC |
| 中文描述： | 8位八路，4象限乘法，BiCMOS工藝援 |
| 文件頁數： | 9/10頁 |
| 文件大?。?/td> | 134K |
| 代理商： | SP9843BS |
265
The four digital control input pins have been
designed to accept TTL (0.8V to 2.0V minimum)
or full 5V CMOS input levels. The serial data
output can drive either TTL or CMOS inputs.
Timing information is shown in
Figure 3
. Serial
data is fully clocked into the shift–register after 12
clock rising edges, subject to the described setup
and hold times. After the shift–register data is
valid, the LOADH line can be pulsed high to load
data into the desired DAC data register, which
switches the DAC to the new input code. The serial
clock input should not see a rising edge while the
LOADH pulse is high in order to prevent shift–
register data from corruption during data register
loading.
The serial clock and data input pins are designed to be
compatible as slaves under
National Semiconductor
's
Microwire and MicrowirePlus protocols and
under
Motorola
's SPI and QSPI protocols. In
some micro–controllers, the interface is completed by
programming a bit in a general–purpose I/O port as a
level, used to strobe the LOADH line at the DACs.
This is done in a manner similar to that used for
generating a Chip Select signal, which is necessary
when driving some other Microwire peripherals.
Figure 3. Timing
CHARACTERISTICS
(Typical @ 25
°
C with V
DD
= +5V unless otherwise noted.)
PARAMETER
Input Clock Pulse Width (t
CH
, t
CL
)
Data Setup Time (t
DS
)
Data Hold Time (t
)
CLK to SDO Propagation Delay (t
PD
)
DAC Register Load Pulse Width (t
LD
)
Preset Pulse Width (t
)
Clock Edge to Load Time (t
)
Load Edge to Next Clock Edge (tLDCK)
MIN.
50
30
20
TYP.
MAX.
UNIT
CONDITIONS
ns
ns
ns
ns
ns
ns
ns
ns
100
50
50
30
60
1
0
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
0
1
0
FS
0
SDI
CLOCK
LOAD
V
OUT
1
0
1
0
1
0
(FF
H
)
(08
H
)
SERIAL
DATA IN
SERIAL DATA INPUT TIMING DETAIL (PRESET = Logic "1"; V
IN(X)
= 1.5V; V
REF
L = 0V)
1
0
SERIAL
DATA OUT
CLOCK
LOAD
V
OUT
t
DS
t
CH
t
CL
t
LD
t
S
t
LDCK
±1 LSB
ERROR BAND
t
CLKD
t
PD
t
DH
A
X
or
D
X
1
0
PRESET
t
S
t
PR
±1 LSB
ERROR BAND
(FF
H
)
(08
H
)
V
OUT
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