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參數(shù)資料
| 型號： | SP97504DG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 4-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDIP18 |
| 封裝： | CERAMIC, DIP-18 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 234K |
| 代理商： | SP97504DG |
SP97504
4
Fig.10 Timing diagram
OPERATING NOTES
1. Carry output (pin 15) is high when the analog input
exceeds the top reference voltage (pin 17)
Then the carry gate outputs (pins 10 to 13) go low
regardless of carry input (pin 4), when the analog input is
between V
REF
and V
REF2
and the carry output is low. The
carry gate output will be high if the carry input is also high.
Similarly if the carry input is low then the carry gate outputs will
be low.
2. When used in an ambient temperature in excess of 65
°
C
the SP97504 must be provided with an external heatsink or
forced air cooling. This will ensure that the junction
temperature does not exceed 175
°
C.
APPLICATION NOTES
1. The SP97504 is ideally suited to subranging systems as it
maintains good accuracy at low reference voltages. This
enables the second rank to be driven at higher speed from the
subtracting Op-Amp
2. For applications that require low bit error rates at high
frequency, the clock signal should be adjusted for 60% ECL
low, 40% ECL high mark to space ratio.
3. The SP97504 is ideally suited to applications in
communication systems that incorporate multi-level coding
(quadrature amplitude modulation).
4. The SP97504 requires a fast edge speed clock. Rise and
fall times of <4ns are recommended.
INPUT LATCHED
OUTPUT LATCHED
LATCH TO
OUTPUT DELAY
DATA
UNCERTAIN
8ns
LATCH
IN
DATA
OUT
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