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參數(shù)資料
| 型號(hào)： | SP4082EEN-L |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX RS485/RS422 8NSOIC |
| 標(biāo)準(zhǔn)包裝： | 98 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | RS422/RS485 |
| 電源電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 管件 |
| 其它名稱： | 1016-1157-5 |
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (50)6687000 Fax (50)668-707 www.exar.com
SP4082E_00_22007
Note: Receiver inputs -200mV < VA - VB < -40mV, should be considered indeterminate
DESCRIPTION
DETAILED DESCRIPTION
The SP4082E is a 5V half-duplex RS-485 trans-
ceiver.
The SP4082E contains one driver and one re-
ceiver. These devices feature fail-safe circuitry
that will guarantee a logic-high receiver output
when the receiver inputs are open or shorted.
The SP4082E features reduced slew-rate driv-
ers that minimize EMI and reduce reflections
caused by improperly terminated cables, allow-
ing error-free data transmission up to 5kbps.
It operates from a single 5.0V supply. Drivers
are output short-circuit current limited. Ther-
mal-shutdown circuitry protects drivers against
excessive power dissipation. When activated,
the thermal-shutdown circuitry places the driver
outputs into a high-impedance state.
Receiver FAILSAFE
Ordinary RS-485 differential receivers will be in
an indeterminate state whenever A - B is less
than ±200mV. This situation can occur when-
ever the data bus is not being actively driven.
The Failsafe feature guarantees a logic-high re-
ceiver output if the receiver’s differential inputs
are shorted or open-circuit.
The receiver thresholds of the SP4082E are
very precise and offset by at least a 40mV noise
margin from ground. This results in a logic-high
receiver output at zero volts input differential
while maintaining compliance with the EIA/TIA-
485 standard of ±200mV.
±15KV ESD PROTECTION
ESD-protection structures are incorporated on
all pins to protect against electrostatic discharg-
es encountered during handling and assembly.
The driver output and receiver inputs have ex-
tra protection against static electricity. Sipex
uses state of the art structures to protect these
pins against ESD of ±5kV without damage.
The ESD structures withstand high ESD in all
states: normal operation, shutdown, and pow-
ered down. After an ESD event, the SP4082E
keeps working without latch-up or damage.
ESD protection can be tested in various ways.
The transmitter outputs and receiver inputs of
the SP4082E is characterized for protection to
the following limits:
±5kV using the Human Body Model
ESD TEST CONDITIONS
ESD performance depends on a variety of con-
ditions. Contact Sipex for a reliability report
that documents test setup, methodology and
results.
MACHINE MODEL
The machine model for ESD tests all pins using
a 200pF storage capacitor and zero discharge
resistance. The objective is to emulate the
stress caused when I/O pins are contacted by
handling equipment during test and assembly.
256 TRANSCEIVERS ON THE BUS
The standard RS-485 receiver input imped-
ance is 12kΩ (1 unit load). A standard driver
can drive up to 32 unit loads. The SP4032E has
only a /8th unit load receiver input impedance
(96kΩ), thereby allowing eight times as many,
up to 256, transceivers to be connected in par-
allel on a communication line. Any combination
of these devices and other RS-485 transceivers
up to a total of 32 unit loads may be connected
to the line.
LOW POWER SHUTDOWN MODE
Low-power shutdown mode is initiated by bring-
ing both RE high and DE low simultaneously.
While in shutdown devices typically draw only
50nA of supply current. DE and RE may be tied
together and driven by a single control signal.
Devices are guaranteed not to enter shutdown
if RE is high and DE is low for less than 50ns. If
the inputs are in this state for at least 600ns, the
parts are shutdown.
Enable times tZH and tZL apply when the part is
not in low-power shutdown state. Enable times
tZH(SHDN) and tZL(SHDN) apply when the parts
are shut down. The drivers and receivers take
longer to become enabled from low power shut-
down mode tZL(SHDN) and tZL(SHDN) than from
driver/receiver-disable mode (tZH, tZL).
DRIVER OUTPUT PROTECTION
Two mechanisms prevent excessive output cur-
rent and power dissipation caused by faults or
by bus contention. First, a driver current limit
on the output stage provides immediate protec-
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