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參數(shù)資料
| 型號(hào)： | SP385EET-L/TR |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 14/15頁 |
| 文件大小： | 0K |
| 描述： | IC DVR/RCVR RS232 18WSOIC |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | RS232 |
| 電源電壓： | 3 V ~ 5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 18-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 18-SOIC |
| 包裝： | 帶卷 (TR) |
8
Exar Corporation 48720 Kato Road, Fremont CA, 94538 510-668-7017 www.exar.com
SP385E_100_030811
Charge Pump
The charge pump is a Exar–patented design
(5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external capaci-
tors, but uses a four–phase voltage shifting
technique to attain symmetrical 10V power
supplies. There is a free–running oscillator
that controls the four phases of the voltage
shifting. A description of each phase follows.
Phase 1
— V
SS charge storage —During this phase of
the clock cycle, the positive side of capacitors
C1 and C2 are initially charged to +5V. Cl+
is then switched to ground and the charge in
C1– is transferred to C2–. Since C2+ is con-
nected to +5V, the voltage potential across
capacitor C2 is now 10V.
Phase 2
— V
SS transfer — Phase two of the clock con-
nects the negative terminal of C2 to the V
SS
storage capacitor and the positive terminal of
C2 to ground, and transfers the generated
–l0V to C3. Simultaneously, the positive side of
capacitor C 1 is switched to +5V and the nega-
tive side is connected to ground.
Phase 3
— V
DD charge storage — The third phase of
the clock is identical to the first phase — the
charge transferred in C1 produces –5V in the
negative terminal of C1, which is applied to the
negative side of capacitor C2. Since C2+ is at
+5V, the voltage potential across C2 is l0V.
Phase 4
— V
DD transfer — The fourth phase of the
clock connects the negative terminal of C2
to ground, and transfers the generated l0V
across C2 to C4, the V
DD storage capacitor.
Again, simultaneously with this, the positive
side of capacitor C1 is switched to +5V and
the negative side is connected to ground, and
the cycle begins again.
Since both V+ and V– are separately gener-
ated from V
CC; in a no–load condition V+ and
V– will be symmetrical. Older charge pump
approaches that generate V– from V+ will
show a decrease in the magnitude of V– com-
pared to V+ due to the inherent inefficiencies
in the design.
The clock rate for the charge pump typically
operates at 15kHz. The external capacitors
can be as low as 0.1F with a 16V breakdown
voltage rating.
Figure 1. Charge Pump Waveform
+10V
a) C2+
GND
b) C2–
–10V
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