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參數(shù)資料
| 型號： | SP3508EF-L |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 21/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX MULTIPROTOCOL 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 8/8 |
| 規(guī)程： | 多協(xié)議 |
| 電源電壓： | 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1154 |
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Exar Corporation 48720 Kato Road, Fremont CA, 94538 (50)668-707 www.exar.com
SP3508_00_072208
Phase 2
-V
SS transfer -Phase two of the clock connects the negative terminal of C2 to the VSS storage
capacitor and the positive terminal of C2 to ground, and transfers the negative generated
voltage to C
VSS. This generated voltage is regulated to -5.5V. Simultaneously, the positive
side of the capacitor C is switched to V
CC and the negative side is connected to ground.
FEATURES
Phase 3
-V
DD charge storage -The third phase of the clock is identical to the first phase-the charge
transferred in C produces -V
CC in the negative terminal of C which is applied to the negative
side of the capacitor C2. Since C2+ is at V
CC, the voltage potential across C2 is 2xVCC.
V CC = +3V
–6V
V SS Stora ge C apacitor
V DD Stora ge C apacitor
C 1
C 2
+
–
C VDD
C VSS1
Figure 46. Charge Pump - Phase 2.
V CC = +3V
–3V
+3V
–3V
V SS1 Storage C apacitor
V DD Storage C apacitor
C 1
C 2
+
–
C VSS1
C VDD
Figure 47.Charge Pump - Phase 3.
-V
DD transfer -The fourth phase of the clock connects the negative terminal of C2 to ground,
and transfers the generated 5.5V across C2 to C
VDD, the VDD storage capacitor. This voltage
is regulated to +5.5V. At the regulated voltage, the internal oscillator is disabled and simulta-
neously with this, the positive side of capacitor C is switched to V
CC and the negative side
is connected to ground, and the cycle begins again. The charge pump cycle will continue as
long as the operational conditions for the internal oscillator are present. Since both V+ and
V- are separately generated from V
CC; in a no-load condition V+ and V- will be symmetrical.
Older charge pump approaches that generate V- from V+ will show a decrease in the mag-
nitude of V- compared to V+ due to the inherent inefficiencies in the design. The clock rate
for the charge pump typically operates at 250kHz. The external capacitors can be as low as
F with a 6V breakdown voltage rating.
Phase 4
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