參數(shù)資料
型號： SP334CT-L/TR
廠商： Exar Corporation
文件頁數(shù)： 12/13頁
文件大?。?/td> 0K
描述： IC TXRX RS232/485 PROG 28WSOIC
標準包裝： 1,500
類型： 收發(fā)器
驅(qū)動器/接收器數(shù)： 3/5
規(guī)程： RS232，RS485
電源電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
8
Exar Corporation 48720 Kato Road, Fremont CA, 94538 50-668-707 www.exar.com
SP334_00_090909
+5V
GND
TTL/CMOS
0V
0.1F
VCC
V+
V-
0V
RXEN
TTL/CMOS
T1
T2
T3
TX1
TX2
TX3
TI1
TI2
TI3
RI1
RI2
RI3
RI4
RX1
RX2
RX3
RX4
1
7
5
6
8
10
C1+
C1-
C2+
C2-
9
11
12
13
14
15
16
17
18
19
20
21
22
RS232/RS485
25
26
27
28
R1
R2
R3
R4
5K
Vcc
RS-232
0V
SP334
0.1F
400K
5K
TTL/CMOS
0.1F
C1+
C1-
C2+
C2-
2
+5V
VCC
5
GND
8
9
11
12
13
19
26
27
1
TTL/CMOS
T1
T3
R1
RS-485
V+
V-
+5V
RS232/ RS485
RS-485
4
6
7
10
14
16
15
25
3
RI2
RI1
TX3
TX4
TX1
TX2
TI1
TI3
RX1
TTL/CMOS
21
R3
17
18
RI4
RI3
RX3
RXEN
15K
400K
Vcc
400K
Vcc
RS-485
SP334
15K
0.1F
TXEN
TTL/CMOS
3
2
4
N/C
R5
5K
RI5 24
RS-232
RX5
23
TTL/CMOS
RS-232 MODE
RS-485 MDDE
Figure 2. Typical Operating Circuit
THEORY OF OPERATION
The
SP334 is made up of four separate
circuit blocks — the charge pump, drivers,
receivers, and decoder. Each of these circuit
blocks is described in more detail below.
Charge–Pump
Thechargepumpisa
Exar–patenteddesign
(U.S.5,306,954)andusesauniqueapproach
compared to older less efficient designs.
The charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 0V
power supplies. Figure 7(a) shows the
waveform found on the positive side of
capacitor C2, and Figure 7(b) shows the
negative side of capacitor C2. There is a
free–running oscillator that controls the four
phases of the voltage shifting. A description
of each phase follows.
Phase 1
— V
SS charge storage —During this phase of
theclockcycle,thepositivesideofcapacitors
C
and C2 are initially charged to +5V. C
+
is
then switched to ground and charge on
C
–
is transferred to C
2
–
. Since C
2
+
is con-
nected to +5V, the voltage potential across
capacitor C
2 is now 0V.
Phase 2
— V
SS transfer — Phase two of the clock con-
nects the negative terminal of C
2 to the VSS
storage capacitor and the positive terminal
of C
2 to ground, and transfers the generated
–l0V to C
3. Simultaneously, the positive side
of capacitor C
is switched to +5V and the
negative side is connected to ground.
Phase 3
— V
DD charge storage — The third phase
of the clock is identical to the first phase
— the charge transferred in C
produces
–5V in the negative terminal of C
, which
is applied to the negative side of capacitor
C
2. Since C2
+
is at +5V, the voltage potential
across C
2 is l0V.
Phase 4
— V
DD transfer — The fourth phase of the
clock connects the negative terminal of C
2
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