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參數(shù)資料
| 型號： | SP3249EEY-L/TR |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 16/16頁 |
| 文件大小： | 0K |
| 描述： | IC TXRX RS232 INTELLIGNT 24TSSOP |
| 產(chǎn)品變化通告： | Packaging Change 15/Jul/2010 |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 5/3 |
| 規(guī)程： | RS232 |
| 電源電壓： | 3 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
Exar Corporation 48720 Kato Road, Fremont CA, 94538 510-668-7017 www.exar.com
SP3249E_100_013111
9
Phase 2
— V
SS transfer — Phase two of the clock
connects the negative terminal of C
2 to the VSS
storage capacitor and the positive terminal of
C
2 to GND.
This transfers a negative gener-
ated voltage to C
3. This generated voltage is
regulated to a minimum voltage of -5.5V.
SimultaneouswiththetransferofthevoltagetoC
3,
the positive side of capacitor C
1 is switched to VCC
and the negative side is connected to GND.
Phase 3
— V
DD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C
1 produces –VCC in the negative
terminal of C
1, which is applied to the negative
side of capacitor C
2. Since C2
+
is at V
CC, the volt-
age potential across C
2 is 2 times VCC.
Phase 4
— V
DD transfer — The fourth phase of the clock
connects the negative terminal of C
2 to GND,
and transfers this positive generated voltage
across C
2 to C4, the VDD storage capacitor. This
voltage is regulated to +5.5V. At this voltage,
the internal oscillator is disabled. Simultane-
ous with the transfer of the voltage to C
4, the
positive side of capacitor C
1 is switched to VCC
and the negative side is connected to GND, al-
lowing the charge pump cycle to begin again.
The charge pump cycle will continue as long
as the operational conditions for the internal
oscillator are present.
Since both V+ and V– are separately generated
from V
CC, in a no–load condition V
+
and V– will
be symmetrical. Older charge pump approaches
that generate V– from V+ will show a decrease in
the magnitude of V– compared to V+ due to the
inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 500kHz. The external capacitors
can be as low as 0.1F with a 16V breakdown
voltage rating.
Figure 10. Charge Pump Waveform
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